JPS63129430A - Microprogram controller - Google Patents

Abstract

PURPOSE:To suppress the number of signal lines or terminals used for only a test operation, by transferring an arbitrary microprogram with a pair of dedicated signal lines, and executing the test operation. CONSTITUTION:A serial/parallel converter 101 shifts the content of a serial input d-in by one bit to the right by generating a shift signal SCLOCK, and a shifted parallel output is outputted to a data bus 220 for microinstruction transfer in a microprogram controller 200. A parallel/serial converter 102 loads the content of a microprogram counter 211 in the microprogram controller 200 at the time of generating a load signal PLOAD, and shifts it by one bit to the right in order by the generation of the shift signal SCLOCK, and outputs overflowed bit data to a serial output d-out. A conversion control circuit 103 generates the shift clock signal SCLOCK that is a timing control signal for the serial/parallel converter 101 and the parallel/serial converter 102, the load signal PLOAD, and an end signal SEND at every generation of a test clock signal TCIN.

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to a microprogram controller.

[Conventional technology]

When a microprogram control method is adopted as a control method for an information processing device, the microprogram may be changed during debugging of the microprogram or testing of the information processing device, or part of the microphone convex program (one or more microinstructions) It may be necessary to execute the following.

Memory that microprograms can read/write (R
AM), it is relatively easy to change the already prepared microprogram, but on the other hand, it is difficult to load the microprogram from another storage device before the information processing device starts operating. The need for and RA
Since M has a low packaging density and is expensive, it is generally stored in a non-rewritable read-only memory (ROM). When a microprogram is stored in a ROM, there is a drawback that its contents cannot be easily changed to change the program.

In order to debug or test a pre-stored micro-program, the following method has conventionally been used to execute a partial micro-program. 1 is a diagram illustrating a conventional microprogram controller for execution; FIG. This conventional microprogram control device includes a microinstruction generation unit 201 that sequentially generates microinstructions, a control signal for the microinstruction generation unit 201, and a control signal (hereinafter referred to as microorder) from the generated microinstructions to the outside of the microprogram control device. The microprogram sequence controller 202 is configured to generate a microprogram sequence control section 202 (referred to as a microprogram sequence controller).

Here, the configuration and operation of the microinstruction generating section 201, which is involved in the main purpose of this conventional example, will be explained.

The microinstruction generation unit 201 includes a microprogram memory 21O that stores a microprogram in advance and reads out a specified microinstruction, and a microprogram counter that specifies the address of the microinstruction stored in the microprogram memory 210. 211,
A microinstruction register 212 that temporarily holds microinstructions supplied from the external data bus 220 of the microinstruction generation unit 201, and a microprogram memory 21.
A multiplexer 213 that selectively outputs the output of 0 or the output of the microinstruction register 212, a microinstruction latch 214 that latches the contents of the multiplexer 213 and temporarily holds the microinstruction to be executed next, and holds it in the microinstruction latch 214. The test control circuit 216 includes a microinstruction invalidation circuit 215 for changing a microinstruction that has been executed into an invalid microinstruction (no-operation NOP), and a test control circuit 216 for generating control signals for the above-mentioned components. A microinstruction to be executed next is generated on the bus 221.

Next, control signals for controlling each component of the microinstruction generating section 201 will be explained. Latch signal STB
is a selection signal M, which is a signal for latching the contents of the data bus 220 into the microinstruction register 212 in order to import a microinstruction into the microinstruction generation unit 201 from the outside.
ODE is a signal for selecting the input of the multiplexer 213, and when it is 0, the microprogram memory 21
This signal selects the output of 0 and the output of the microinstruction register 212 when it is 1°. The latch signal LCH is a signal for latching the output of the multiplexer 213 into the microinstruction latch 214 in order to temporarily hold the microinstruction to be executed next. In order to disable execution, the output of the microinstruction latch 214 is left as is in the case of °O゛, and the output of the microinstruction latch 214 is
This is a signal for outputting a microinstruction equivalent to a NOP instruction (related to the contents of the NOP instruction).

Next, the operation of this conventional example will be explained with reference to the timing chart of FIG. 7, especially the operation of executing a microinstruction other than a previously stored microprogram. Here, an operating mode that executes a previously stored microprogram is called a normal operating mode, and an operating mode that executes other microinstructions is called a test operating mode.

In the normal operation mode, the selection signal MODE is set to 0°, and the output of the microprogram memory 210 pointed to by the contents of the microprogram counter 211 is sent to the microinstruction latch 214 by the latch signal L (:11
Latched on occurrence. In addition, if an invalid microinstruction is latched in the microinstruction latch 214, such as immediately after a branch microinstruction, the control signal TNH becomes °l, and the microinstruction latched in the microinstruction latch 214 is converted into a NOP instruction. Replace with If the microinstruction latched in the microinstruction latch 214 is not a branch instruction, the microprogram counter 211 is incremented by 1 after the execution of the microinstruction, and the microinstructions stored at the next address are sequentially transferred to the microinstruction latch 214.
and sequentially executes the microinstructions stored in the microprogram memory 210.

In the test operation mode, microinstructions to be executed are stored in advance in the microinstruction register 212 via the data bus 220.
It is latched by a latch signal STB via a latch signal STB.

This latching operation can be performed at any time regardless of the operating mode. When the test operation mode is switched, the selection signal MODE is set to 1', and when the latch signal LCH is generated, the contents of the microinstruction register 212 are latched into the microinstruction latch 214. After executing the microinstruction latched in the microinstruction launcher 214, the microprogram counter 211
The contents of is incremented by 1, but no engraving is given to the next microinstruction to be executed. That is, the selection signal M
While ODE is °l°, microprogram memory 2
The microinstruction stored in microinstruction latch 10 is
This is because it never latches to 14.

Before the execution of the microinstruction latched by the microinstruction latch 214 is completed, the microinstruction register 212 must latch the microinstruction to be executed next via the data bus 220. Basically, one microinstruction completes execution in one basic clock period, so the microinstruction register 212 must also be updated with a new microinstruction every wood clock. If a new microinstruction cannot be latched from the microinstruction latch 214, the control signal INH is set to 1 in order to invalidate the microinstruction stored in the microinstruction latch 214 until the latch operation is completed. Even if the supply of microinstructions is slow, the test operation mode can be implemented without any problems.

FIG. 8 is a diagram showing an example in which this conventional example is applied to a central processing unit.

The CPU 401 has an address path 8n, a data bus 0
It is connected to a main storage device 402, an input device 403, and an output device 404 via n. The control signal group Cn output from the CPU 401 is connected to the control device 405,
Main storage device 402, input device 403 and output device 40
A signal controlling 4 is issued. Micro program/
The test device 410 includes a bus diag-bus for transferring microinstructions to and from the CPU 401.
Operation mode selection signal DIAG MOD for controlling the operation mode of the microprogram controller 200 in
E. Connected by a timing signal DIAG VALID indicating that data on the bus diag-bus is valid, microinstructions can be transferred to the microprogram control device 200 in the CPU 401 and executed at any time. .

Next, the operation of this application example will be explained with reference to FIG. 9 showing the operation timing of this application example.

In the normal operating mode, the microprogram tester 410 sets the operating mode selection signal DIAG MODE to 0'. Operation mode selection signal CIAGMO
DE is directly connected to the microprogram control device 200 as a MODE signal, and the microprogram control device 200 operates without being influenced by the microprogram test device 410.

In the test operation mode, the operation mode selection signal DIAG
MODE is set to 1. At this point, the timing signals DI to GV to LID become 0, indicating that the data on the data bus diag-bus is invalid. The test control circuit 216 in the microprogram control device 200 sets the control signal INN to °l'' to inhibit (disable) execution of the microinstruction latched in the microinstruction latch 214 for next execution. When the microinstruction to be tested is ready in the controller 405, it is output to the data bus diag-bus and to the microinstruction register 212 via the external data bus 220.At this point, the timing signal DIAG When VALID becomes 1, the test control circuit 21G generates a latch signal ST[l,
The contents of the external data bus 220 are transferred to the microinstruction register 2.
Latch to 12.

Subsequently, the control signal IN+1 is set for one basic tarok period °0
By setting it to .degree., the microinstruction latched from the microinstruction register 212 to the microinstruction latch 214 is executed by validating it for one basic clock period.

The generation of the latch signal STB and the temporary release of the control signal INH are not performed until the next timing signal transitions from "0" to "1".
There is no need to prepare the next microinstruction to be executed every basic clock.

As explained above, in the test operation mode, the microprogram test device 410 sequentially outputs microinstructions to the data bus diag-bus and inverts the timing signal DIAG VALID, thereby sequentially testing microprograms other than those prepared in advance. It can execute microinstructions.

By the way, in the above application example, the microinstructions input to the CPU 40 are sent to the dedicated data bus diag-b.
However, microinstructions with advanced functions generally have a long bit width of 20 bits or more, and the data bus diag-bus must have a bit width of that much. No.

Pulling out many signal lines from an information processing device results in an increase in the amount of wiring and the number of terminals. In particular, when the functions of an information processing device are integrated into a single LSI such as a microprocessor, there is a certain limit on the number of terminals, that is, the number of bins. Allocating dedicated bins to signals that are only used in the network incurs high costs. As a method of transferring microinstructions to the information processing device in the test operation mode, there is a method of dividing the data bus diag-bus into several fields based on the bit width of the microinstructions and transferring them in a time-sharing manner. It is unavoidable that a data bus must be provided.

Therefore, as shown in Fig. 10 as an improved application example,
Data and microinstruction transfer during test operation mode
A possible method for the bus diag-bus is to share a signal line used in the normal operation mode. In this application example,
The data bus 220 is used as a data bus 220 to transfer microinstructions to the microprogram control device 200 in the CPU 421, and the bus 422 is used mainly to transfer addresses of operands in the normal operation mode, and the bus 422 is used to transfer commands to components other than the microprogram control device 200. A bus 423 is used to transfer the information. The reason why multiple buses are used is that the bit width of a microinstruction is wider than the bit width of bus 422 or bus 423.

In addition, not using a dedicated bus means that extra hardware resources (wiring is also an important hardware resource, especially in LSIs, are an important factor in determining chip size) in addition to the normal operation mode. This is to avoid doing so.

Bus 422 and bus 423 are connected to address bus An and data bus Dn during the test operation mode. Microprogram test device 430 can transfer microinstructions into CPU 421 by outputting necessary microinstructions to address bus An and data bus On.

In the improved conventional application described above, the increase in dedicated hardware for transferring microinstructions during the test operation mode can be kept to a minimum.

By the way, in the improved conventional application example, external addresses and
bus An, data bus On and internal bus 422,
423, it has the disadvantage that microinstructions that use these resources cannot be executed, and arbitrary microinstructions cannot be tested.

In addition, the conventional microprogram control device 200 described above can only execute microinstructions regardless of the internal state of the CPU 401 or 421, that is, under the condition that the internal state is judged and the sequence of the microprogram is changed. The disadvantage is that the execution results of branch microinstructions cannot be known externally.

After transferring the conditional branch microinstruction from outside and executing it,
If the condition is satisfied, the next branch destination microinstruction is
If a condition is not satisfied, another instruction must be transferred from the outside, but if the internal state cannot be known from the outside, these selective microinstruction transfers cannot be performed.

Therefore, conventionally, it has been impossible to transfer and execute a complex microinstruction sequence from the outside, and it is only possible to execute a simple microphone and mouth command sequence using microinstructions that are limited in type.

[Problem that the invention seeks to solve]

In the conventional microprogram controller described above, dedicated data with a long bit width is used to transfer the microinstruction to be tested to the microprogram controller.
bus, and therefore requires a large amount of hardware dedicated to the test function, or the number of microinstructions that can be tested is limited.Furthermore, testing relatively complex microinstruction sequences The disadvantage is that it is impossible to

[Means for solving problems]

The microprogram control device of the present invention includes a serial/parallel converter that converts microinstructions transferred as serial data into parallel data, and a parallel/serial converter that converts the internal state of the microprogram control device into serial data. transmitting a microinstruction to the serial/parallel converter as serial data; simultaneously transmitting the internal state of the microprogram controller to the parallel/serial converter as serial data; and transmitting the serial data. The present invention is characterized in that it includes a conversion control circuit that causes the serial/parallel converter to execute the microinstructions stored in the serial/parallel converter when the conversion is completed.

In contrast to the conventional microinstruction control device described above, the present invention transfers test instructions through a minimum number of dedicated signal lines in the test operation mode, does not limit the microinstructions to be tested, and furthermore, the present invention transfers test instructions using a minimum number of dedicated signal lines. This makes it possible to trace the sequence of

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the microprogram control device of the invention, and FIG. 2 is a timing chart thereof.

In the unimplemented example, the contents of the serial input d-in are shifted to the right by 1 bit by the generation of the shift signal 5CLO (J), and the shifted parallel output is transferred to the data bus 220 for microinstruction transfer of the microprogram controller 200. The contents of the output serial/parallel converter 101 and the microprogram counter 211 in the microprogram control device 200 are loaded when the load signal PLOAD is generated, and when the shift signal 5CLQCK is generated, the contents are sequentially shifted one bit to the right to prevent overflow. The parallel/serial converter 102 outputs bit data to the serial output d-out, and the timing control of the serial/parallel converter 101 and the parallel/serial converter 102 is performed every time the test clock signal T[:IN is generated. Shift clock signal 5CLOCX, load signal PL
It is composed of a conversion control circuit +03 that generates OAD and an end signal 5END.

It should be noted that the microprogram memory 210
microinstructions stored on the data bus 22 as well as microinstructions stored on the data bus 22
Assume that the hit width of 0 is 37 bits and the bit width of microprogram counter 2]1 is 16 bits. In this case, the bit width of the serial/parallel converter 101 is 3
The bit width of the 7-bit parallel/serial converter 102 is 16 bits.

Next, the operation of this embodiment will be explained with reference to FIG.

Timely word 5 CLO, PLO eight and 5
END occurs as follows depending on how many times the test clock signal TCIN is issued to the conversion M] control circuit +03.

■11th...Load signal PLOAD■2
~38th time...Shift clock signal 5CLO (J■
38th time... End signal 5END When the test clock signal TCIN is issued up to the 38th time, the test clock (No. 8 TCIN is treated as having been issued from the first time. In other words, 38 Each time the test clock signal TCIN is generated, the timing signals PLOAD and 5CL are generated according to the rules ① to ③ above.
OCK and 5END are issued.

The shift clock signal 5CLO (:K) generated when the test clock signal TCTH occurs for the 2nd to 38th time When a 37-bit wide microinstruction to be tested is input in order starting from the least significant hit (LSB), after the 38th test clock signal TCIN is generated, the serial/parallel converter +01 has the complete microinstruction to be tested. is set.

The fact that a microinstruction to be tested is set in the serial/parallel converter 101 is detected by the generation of the end signal 5END.

Microprogram: tl (J When the control device 200 is operating in the test operation mode, the microinstruction output to the data bus 220 is executed for one basic clock period in synchronization with the end signal 5END.

When the next 38 test clock signals TCIN are input, the transfer of the next microinstruction to be tested is completed, and this microinstruction is executed.

Next, the shift output d-out will be explained. The current contents of the microprogram counter 211 are set in the parallel/serial converter 102 by the rotat signal PIOAD generated when the test clock signal TCIN is generated for the first time. Shift signal 5 issued with subsequent generation of test clock signal Tcui
Parallel/serial converter 102 in synchronization with CLOCK
The contents of d-out are shifted 1 bit at a time, and the overflowing hit data is outputted to the shift output d-out, 61 bits at a time. That is, when the load signal PI, 0^D is issued, the contents of the microprogram counter 211 latched are shifted out from the LSB in synchronization with the shift signal S (:LOCK, that is, the test clock signal TCIN).
Output from out.

However, since the bit width of the parallel/serial converter 102 is 16 bits, the bit width of the parallel/serial converter 102 is 16 bits.
After the contents of are completely shifted out from the shift outputs d-out and t, that is, in synchronization with the test clock signal TCIN from the 17th time onwards, a constant value 0° is output from the shift output d-out. Ru.

Further, the contents of the microprogram counter 211 do not change unless a microinstruction is executed, and in the °'cheest operation mode, no microinstruction is executed unless the end signal 5END is issued. Therefore, after the load signal PLOAD is issued once, the next load signal PLOAD
Microprogram counter 2 until AD is issued.
The contents of 11 will never change excessively (it will be incremented by 1 or the tested branch microinstruction will have a value other than the specified value), and it will always be the execution result of the test microinstruction executed immediately before. The value of the microprogram counter 211 that reflects the shift output d-out
is output from.

Next, an example of application of this embodiment to a microprogram control device built into a central processing unit will be described. FIG. 83 is a diagram showing the configuration of a CPU 701 and a microprogram test device 702 using the microprogram control device 100 employing the above embodiment.

CPU 701 and microprogram test device 702
They are connected by an operation mode selection signal DIAG MODE, a timing signal DIAG VALID, and serial signals diag-in and diag-out. G MODE to the operation mode selection signal DI is
It has the same function as DIAG-MODE in the conventional information processing apparatus shown in FIGS. 8 and 10. That is, it is a signal for specifying whether the microprogram control device 100 is operated in the normal operation mode or the test operation mode. timing signal DI
AG_VID is directly connected to test clock signal TCIN. Similarly, the serial signal diag-in is directly connected to the serial input d-in, and the diag-out is directly connected to the serial output d-out.

In the test operation mode, the microprogram control device 100 sequentially outputs 38 DIAG VALID signals and test microinstructions decomposed into 37 bits from the LSB to the serial input drag-in. It can execute one arbitrary microinstruction. Also, 2-1
In synchronization with the issuance of the DIAG VALID signal up to the seventh time, the contents of the microprogram counter 211, which reflects the execution result of the previous microinstruction, are serially output diag-out as 16-bit serial data.
is output to. Microprogram test device 702
Now, 3 output from the serial output diag-out
Extract the first 16 bits from the 7-bit serial data and set the value of the microprogram counter 211 to 16.
By reproducing it as bit data, it is possible to know the value of the microprogram counter 211 that reflects f12'J, the execution result of the microinstruction tested immediately before.

Therefore, the microprogram test device 702 is not only capable of transferring and testing any microinstruction regardless of the internal state of the microprogram control device 100, but also if the microinstruction being tested is a conditional branch instruction, When the next test microinstruction is transferred and executed, the branch destination can be determined by knowing from the value of the microprogram counter 211 whether the branch condition was satisfied and the branch operation was performed, or whether the branch condition was not satisfied. Alternatively, microinstructions corresponding to sequential addresses (the contents of the immediately preceding microprogram counter 211 incremented by one) can be selectively transferred and tested. Furthermore, even if the contents of the microprogram counter 211 change due to reasons other than the control of the microprogram, such as the occurrence of an interrupt, the microprogram test device 702 can detect this, so the operation of the microprogram control device 100 can be detected in detail. can be managed.

FIG. 4 is a block diagram of another embodiment of the invention. This embodiment is characterized in that it has a parallel/serial converter 104 which is the same as the serial/parallel converter 101 in the previous embodiment, that is, has a width of 37 bits.

The contents of the 16-bit wide microprogram counter 2+1 are connected to the lower 16 bits of the parallel input of the parallel/serial converter toll.

The upper 21 bits of the parallel input of the parallel/serial converter 104 are stored in a processor status word register 801 having a width of 32 bits.
The contents of important flags that change frequently or are closely related to program operations are connected. Serial output signal d-
From out, the contents of the microprogram counter 211 are output as serial data in synchronization with the generation of the 2nd to 17th test clock signals TCfN, and the 18th to 388th to 38th test clock signals TCIN
The contents of the flag in the processor status word register 801 are output as serial data in synchronization with the processor status word register 801.

FIG. 5 is a diagram showing the state of the serial output d-out in this embodiment. A shows the state of the serial output d-out in this embodiment, and B shows the state of the serial output d-out in the previous embodiment.

In the test operation mode, the microprogram counter 21 is
In addition to the contents of 1, the contents of the flag in the processor status word register 801 can be transferred, so by analyzing the contents of the output flag, it is possible to transfer the contents of the arithmetic microinstruction that was just executed (tested). You can know the results to some extent.

In this embodiment, serial/parallel converter lot
parallel/serial converter 10 with the same bit width as
4 parallel inputs, microprogram counter 2
] In addition to the contents of 1, the contents of the flag in the processor status word register 801 are connected, but it is also possible to connect another resource in the microprogram control device 200 that changes every time a microinstruction is executed. be.

〔Effect of the invention〕

As described above, the present invention has the following effects by transferring an arbitrary microinstruction through a set of dedicated signal lines and executing a test.

■ By minimizing the number of signal lines or terminals used exclusively for test operations, it is possible to provide an inexpensive microprogram test system. This is particularly effective in cases where the number of terminals is limited in advance, such as in LSIs.

■ Also, since any microinstruction can be executed, there are no restrictions on the microinstructions that can be tested during testing.

■ Furthermore, since the execution status of microprograms can be constantly monitored, it is also possible to test run complex microprograms that contain microinstructions such as conditional branch instructions, where there are multiple microinstructions to be executed next. . Therefore, advanced and highly efficient microprogram debugging or microprogram control device testing can be performed.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of an embodiment of the microprogram control device of the present invention, FIG. 2 is a timing chart of the embodiment of FIG. Drawings, FIG. 4 is a drawing showing the configuration of another embodiment of the present invention,
5 is a timing chart of the embodiment shown in FIG. 4, FIG. 6 is a diagram showing the configuration of a conventional microprogram control device, FIG. 7 is a timing chart of the microprogram control device shown in FIG. 6, and FIG. 8 is a timing chart of the embodiment of FIG. FIG. 6 is a diagram showing the configuration of an application example in which the microprogram control device of FIG. 6 is applied to a central processing unit, FIG. 9 is a timing chart of the application example of FIG. 8, and FIG. 10 is a diagram showing the configuration of another application example. It is. +00...Microprogram control device 101...
Serial/parallel converter 102, 104...Parallel/serial converter 103...Conversion control circuit 200...Microprogram control device 201...
Microinstruction generation unit 202...Microprogram sequence control unit 2
10...Microprogram memory 211...Microprogram counter 212...Microinstruction register 213...Multiplexer 214-...Microinstruction latch 215...Microinstruction invalidation circuit 216...Test control Circuit 220...External data bus 221...Microinstruction bus 701...CPU 702...Microprogram test equipment star Figure 3i Figure 6C

Claims (1)

[Claims] In a microprogram control device that has a built-in means for storing microinstructions, a serial
a parallel converter; a parallel/serial converter for converting an internal state of a microprogram controller into serial data; and a parallel/serial converter for transferring microinstructions as serial data to the serial/parallel converter; The converter further includes a conversion control circuit that transfers the internal state of the microprogram control device as serial data to the converter, and executes the microinstruction stored in the serial/parallel converter when the transfer of the serial data is completed. Features a microprogram control device.