JPS5998256A - Interruption controller - Google Patents

Abstract

PURPOSE:To distinguish easily a maskable interruption and a non-maskable interruption from each other, by providing a means which accepts and processes the non-maskable interruption without the influence upon the state of an interruption permission flag for the maskable interruption. CONSTITUTION:When a non-maskable interruption request signal INT0 is applied, an interruption request flag RQ30 is set. Therefore, a flag EI30 indicating the interruption execution is set, and an OR32 is set to 1 through an FFEX30, and the interruption processing is executed. Since other interruption are inhibited during the execution of the interruption processing, an interruption permission flag EI31 is not changed, and a return instruction RT1 is executed without executing an instruction EI after the execution of the interruption processing, and the control is returned to the original routine. When the instruction RTI is executed, the flag EI30 indicating the execution of the interruption processing for INT0 is reset, and it is determined by the output of the interruption permission flag EI31 whether other interruptions are permitted or not.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an interrupt control device, and particularly to an interrupt control device used in a microcomputer or the like.

In recent years, microcontrollers have been equipped with numerous functions such as storage devices, timers/counters, and serial transmission/reception functions on a single semiconductor substrate.
Combiators were introduced and came to be used for various purposes such as various control equipment. In such a so-called single-chip Φ microcomputer, the CPU
The so-called interrupt processing is known in which a predetermined process is executed preferentially each time by outputting an interrupt request signal to the external interrupt request signal. It is being These interrupts include maskable interrupts that can be masked (i.e., not accepted) by resetting the interrupt enable flag with a command from the CPU, and non-maskable interrupts that cannot be masked. (For example, emergency interruption, etc.) Conventionally, no matter which interrupt occurs, interrupt acceptance sometimes resets the interrupt permission 7 lag. Therefore, when returning to the previous process 70- after executing the non-maskable interrupt process, it is impossible to determine whether to set or reset the interrupt permission flag. Therefore, there is no other way than to provide a flag equivalent to the interrupt permission flag in the storage device and process it software-wise, which makes the program complicated and increases the time required for interrupt processing. There was a drawback.

SUMMARY OF THE INVENTION An object of the present invention is to provide an interrupt control device that can easily distinguish maskable interrupts from non-maskable interrupts, and that can easily return to normal mode after these interrupts are completed.

The present invention is characterized by providing means for accepting and processing non-maskable interrupts without affecting the state of the interrupt permission flag for maskable interrupts.

An embodiment of the present invention will be described below with reference to the drawings.

First, FIG. 1 showing a block diagram of a conventional interrupt control device will be described. INTO~INTn are interrupt request signals, RQIO~RQ1n are interrupt request flags, and EII
I is an interrupt permission flag, and each is a set/reset type flip-flop.

MKII~MKIn are interrupt mask registers, person 10~A
ln is an AND gate, PRII is a priority circuit, OR,
11/0R12 is an or gate, and EXII is a D type slip 70 tube. INTO is a non-maskable interrupt! D, INTl to INTn are maskable interrupts. FIG. 2 shows the interrupt processing sequence. First, mask registers MK11 to MKn are set to logic “0” (hereinafter “
0''), and the interrupt enable flag EIII is set by the EI (interrupt enable) instruction.

This enables all interrupts. Next, lNTl
When the interrupt request signal is applied, RQII is set,
The Q output of RQII is logic “1” (hereinafter abbreviated as “1”),
AND gate A11 is “1”, priority circuit P11
011.0100 and ``1'' of ``1'' and ``1'' are read into the shift flip-flop EXII, and interrupt processing is executed. Since the 011 output of the priority circuit PRLI becomes "1", the 7 lip-flop RQII is reset and enters a waiting state for the next interrupt request signal. Furthermore, the interrupt enable flag EIII is automatically reset by the output of the 7 lip-flop EXII, and interrupts other than the non-maskable interrupt INTO are prohibited. After the execution of the interrupt process is completed and the EI instruction and RTI (return) instruction are executed, the original routine is returned.

However, for the non-maskable interrupt INTO, interrupt processing is executed regardless of the state of flip-flop EIII.

, thereby resetting flip-flop EIII. Therefore, after execution of the interrupt process corresponding to INTO, it is impossible to determine whether to execute the EI instruction or the DI (interrupt inhibit) instruction and return to the original routine using the RTI instruction. Also, a storage device (not shown)
A flag corresponding to the interrupt permission flag EIII is provided in
Although there is a method of processing the interrupt using software, it has the drawbacks that the program becomes extremely complicated and the time required to execute the interrupt processing increases. FIG. 3 is a block diagram showing an embodiment of the present invention, in which interrupt request flags corresponding to N interrupt request signals and fewer than N interrupts for suppressing the output of the interrupt request flags are shown. This interrupt control device has a suppression register, a priority circuit that determines the order of N interrupts, and two means for suppressing all interrupt requests suppressed by the interrupt suppression register. RQ 30-RQ 3 n is an interrupt request flag, EI30 is a non-maskable interrupt INT
A flag indicating that interrupt processing is being executed at O and an interrupt permission flag at EI31 are set/reset type flip-flops. MK31 to MK3n are interrupt mask registers, A30 to A3n are analogue), PR31 is a priority circuit, 0R31 and 0R32 are OR gates, EX30 and
EX31 is a D type flip-flop. FIG. 4 shows the processing sequence of the non-maskable interrupt INTO.

When the INTO interrupt request signal is applied, the interrupt request flag RQ30 is set, the Q output is "1", and the interrupt execution 7 lag EI30 is set and read into the 7 lip-flop EX30. . flip 70 tsugu EX
In response to the output of 30, the OR gate 0R32 becomes "1" and interrupt processing is executed.

Furthermore, when 030 of the priority circuit PR31 becomes "1", the interrupt request request RQ30 is reset. Here, since the 7-lag EI30 is set while the interrupt process is being executed, other interrupts are prohibited and the output of the ant gate A30 is "0".
becomes. Since the interrupt permission flag EI31 does not change at the time of the non-maskable interrupt INTO, the EI instruction is not executed after execution of the interrupt processing, the RTI instruction is actually executed, and the original routine is returned. Furthermore, when the RTI instruction is executed, the INTO interrupt processing execution lag EI30 is reset, and whether other interrupts are enabled or disabled is determined by the output of the interrupt enable flag EI31.

In this way, when non-maskable interrupt processing is executed, the interrupt enable flag is not affected (that is, it is not reset), so even if the original routine is returned after non-maskable interrupt processing is executed, the maskable interrupt enable hook does not change. .

As is clear from the above description, according to the present invention, there is no need to judge which instruction to execute, the EI instruction or the DI instruction, after execution of non-maskable interrupt processing. Further, since there is no need to provide a flag corresponding to an interrupt permission flag in the storage device and perform software processing, program creation is easy and interrupt processing execution time is shortened.

Therefore, it is possible to provide a highly effective and highly versatile interrupt control device for information processing devices such as microcomputers.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional interrupt control device, and FIG.
1 is an interrupt sequence diagram for explaining FIG. 1, FIG. 3 is a block diagram showing an embodiment of the present invention, and FIG.
FIG. 3 is an interrupt sequence diagram for explaining the figure. RQIO~RQ1n, EIII, RQ30~RQ3n
. EI30. EI31...-Set/reset type flip-flop, MKll ~ MKIn, MK31 ~ MK3
n--Register, EXll, EX30, EX31・
...D type flip-flop, Al O~A1
n, A30 to A3n -...and gate, 0
R11, 0R12, 0R31, 0R32......or game), PRII, PR31...Priority circuit.

Claims (1)

[Claims] In an interrupt control device which receives a maskable interrupt request signal and a non-maskable interrupt request signal as input, a means for controlling whether or not to permit each interrupt request is provided independently. An interrupt control device characterized in that: