JPH0287256A - Interruption control system - Google Patents

Abstract

PURPOSE:To efficiently execute interruption processing in the internal part of a processor by providing an interruption control part and preferentially releasing a common bus to the interruption processing based on the interruption request of high priority. CONSTITUTION:An interruption control part 12 is provided to determine the use priority of a common bus 11 in correspondence to the priority of the plural interruption requests. The common bus 11 is preferentially released to the interruption processing based on the interruption request of the high priority. Namely, since the common bus 11 is preferentially released by the interruption control part 12 to the interruption request of the high priority, the interruption processing is preferentially executed by the interruption request of the high priority. Thus, the priority order of the interruption processing goes to be clear and the interruption processing can be efficiently executed.

Description

[Detailed Description of the Invention] Overview Regarding an interrupt control method for controlling interrupt requests for a multiprocessor equipped with a common bus, the purpose of this method is to set usage priority of a common bus according to the priority of interrupt requests. In an interrupt control method that controls interrupt requests for a multiprocessor that has a common bus, an interrupt control unit is provided that determines the priority of using the common bus according to the priorities of multiple interrupt requests, and the interrupt control unit determines the priority of using the common bus according to the priorities of multiple interrupt requests. The common bus is configured to be released preferentially for interrupt processing.

INDUSTRIAL APPLICATION FIELD OF THE INVENTION The present invention relates to an interrupt control method for controlling interrupt requests to a multiprocessor having a common bus.

As computer systems become faster and larger, software and hardware are being developed to use computer systems as efficiently and easily as possible. In the hardware configuration of a system equipped with a microprocessor, a processing device (
There is a multiprocessor method that improves processing power and reliability by arranging multiple processors in parallel and dividing processing functions and performing parallel processing. In this multiprocessor system, when a part of the access area of each processor is shared by each processor, a configuration is adopted in which part of the processor bus is shared (common bus).

In such a multiprocessor, simultaneous access (competition) for a common area by each processor occurs, so arbitration is performed within the system to decide which processor the bus should be given to.

Furthermore, since it is possible to input interrupt requests to each processor asynchronously with the operation of its execution program,
Contention on the common bus of interrupt processing based on each separate request is controlled.

Furthermore, there is a demand for efficient processing of interrupt processing based on interrupt requests within a processor.

Prior Art FIG. 5 shows a block diagram of a conventional interrupt control system.

Connected to the common bus 45 are processors 42 and 43 that operate independently. Each of the processors 42 and 43 has an interrupt source and an interrupt request (
IRQ) is now available. When interrupt processing by IRQ uses the common bus 45, the common bus 45
Since contention occurs, it is necessary to set bus usage priorities for IRQs. However, generally the bus arbitration section 4
4 is a configuration in which a low-priority processor issues a bus request (BUSREQ) to a high-priority processor, and the lower-level processor gains ownership of the bus upon acknowledgment (ACK) and ACK transmission from the higher-level processor. It has become. Therefore, when a common bus conflict occurs, a bus (processor) with a higher priority takes priority over an interrupt process with a higher priority, and the priority of the bus is determined uniformly. For example, if the processor 42 has a higher bus usage priority than the processor 43, the processing of IRQI-1 and IRQI-2 is
It has priority over the processing of Q2-1 and IRQ2-2.

Problems to be Solved by the Invention However, in the conventional interrupt control method as described above, (
Interrupt requests that are prioritized based on the bus usage priority determined for each processor are given priority over interrupt requests with a high priority and use the common bus, so they are originally processed with priority. There is a problem in that processing of high-priority interrupt requests that should be processed is delayed.

For example, the priority of the interrupt request in FIG.
QI-1, IRQ2・-1, IRQI-2, IRQ2-
2, if the bus usage priority determined for each processor is the order of processors 42 and 43, then I
rRQl-2 will be processed more preferentially than RQ2-1.

The present invention has been made in view of these points, and an object thereof is to provide an interrupt control method that can set the usage priority of a common bus according to the priority of interrupt requests.

A means to solve problems FIG. 1 is a block diagram of the principle of the present invention.

In an interrupt control method for controlling interrupt requests for a multiprocessor having a common bus 11 among a plurality of processors 10, an interrupt control unit 12 is provided that determines the priority of use of the common bus 11 according to the priorities of the plurality of interrupt requests. . Then, the common bus 11 is preferentially released for interrupt processing based on an interrupt request with a high priority.

According to the present invention, the interrupt control unit 12 releases the common bus 11 preferentially for interrupt requests with high priority, so that interrupt processing due to interrupt requests with high priority is processed preferentially.

Embodiments The present invention will be explained in detail below based on embodiments shown in the drawings.

FIG. 2 shows a circuit diagram of an embodiment of the interrupt control system according to the present invention, and FIG. 3 shows a schematic block diagram of the circuit shown in FIG.

First, the schematic configuration of the circuit shown in FIG. 2 will be explained using FIG.

A multiprocessor is configured by central processing units (CPUs) 20 and 21, and has a common bus 26. Interrupt requests (IRQ) are sent to these CPUs 20.21.
) manpower is possible. The IRQ signal is latched by the latch circuit 23 and sent to the priority calculation circuit 22 which determines the usage priority of the common bus 26. Also, each I
A common bus use request signal indicating whether or not the RQ uses the common bus 26 is latched by the latch circuit 24 and sent to the priority calculation circuit 22. Bus use (BUS US) informs you of the availability of common bus 26.
E) A signal is sent to the priority calculation circuit 22 via the flip-flop 25. The interrupt request output from the priority calculation circuit 22 is sent to the CPU 20 or 2.
1.

FIG. 4 shows a processing flowchart in the priority calculation circuit, and the processing will be explained below.

When an interrupt request occurs (101), the interrupt request information is latched (102), and the interrupt request is transferred to the common bus 2.
6 is not used (103), the priority calculation circuit 22 outputs the interrupt request (104).
, interrupt processing is performed (1 0 5).

When the interrupt request uses the common bus 26 (103)
, the priority of the interrupt request currently being processed is calculated (106). If the priority of the interrupt request that has occurred is lower than the priority of the interrupt request that is currently being processed (107), the process waits for the interrupt process that is currently being processed to end (108). When the process is finished (109)
, the generated interrupt request is output from the priority calculation circuit 22 (110), and interrupt processing is performed (1
11).

Also, if the priority of the generated interrupt request is higher than the priority of the interrupt request being processed (10
7) The interrupt processing currently being processed is stopped on the common bus 26 (112). Then, the generated interrupt request is output from the priority calculation circuit 22 (11
3), interrupt processing is performed (114).

Next, referring to Figure 2, the interrupt request (IRQ) is
QI to IRQ4, and the priorities of these IRQs are in the order of IRQI, IRQ2, IRQ3, and IRQ4. IRQI and I RQ3 are interrupt requests to the CPU20, and IRQ2 and IRQ4 are interrupt requests to the CPU20.
This is an interrupt request for 1. For IRQI to IRQ4, those IRQs receive common bus use request signals BUSUI to BUSU indicating whether or not to use the common bus 26.
4 is provided. Buffer 34-37.0R circuit 3
8-41, NOT circuits 31-33, AND circuits 28-3
0 and the latch circuit 27, the priority calculation circuit 2
2 are configured.

The BUSUSE signal is input to the D terminal of the flip-flop 25, and the common bus 26 is input to the clock terminal (CK).
Write clock when accessing WRITE
CK) signal is input. When the common bus 26 is being accessed, the IRQ signal cannot be taken in by the CPU 20.21, so when this access is finished,
The Q terminal output is set to low level by a clear terminal (not shown). As a result, the output from the Q terminal becomes high level only at the moment when the bus is being accessed. Further, this Q terminal output is taken in by the latch circuit 27 and determines the sending timing of the IRQ signal sent out from the latch circuit 27.

In general, interrupt processing has a higher priority than normal operation, and such guarding is applied when the bus cannot be released due to processor processing.

The operation of each configuration when the IRQ is latched by the latch circuit 23 will be described.

For example, if the IRQI does not use the common bus 26;
! , BUSUI is at low level, the buffer 34 is
is in the open state, and the IRQI signal is sent to the buffer 34, O
It is latched by the latch circuit 27 via the R circuit 38. Then, when the Q terminal output from the flip-flop circuit 25 is at a low level, an IRQI signal is sent to the interrupt input terminal INTl of the CPU 20, and interrupt processing is performed.

Furthermore, when IRQ2 (using the common bus 26) occurs while performing interrupt processing using the common bus 26 due to IRQI, the buffer 35 is in a closed state, and the IRQ2 signal is passed to the AND circuit 28. One end of and N
The signal is sent to the OT circuit 32. Here, the other end of the AND circuit 28 has an IRQ with a higher priority than IRQ2.
Since the I signal is input manually through the NOT circuit 31, the output from the AND circuit 28 is low level while IRQl is processing an interrupt, and the IRQ2 signal is input to the latch circuit 2.
7 is not sent.

When the IRQI interrupt processing is completed and the IRQI signal becomes low level, the output from the AND circuit 28 becomes high level, the output from the OR circuit 39 also becomes high level, and the IRQ2 signal is latched in the latch circuit 27. Ru. (When the output from the Q terminal of the flip-flop circuit 25 is at a low level and no bus access is being performed)
, is sent to the interrupt input terminal lNTl of the CPU 21,
Interrupt processing using the common bus 26 is performed.

Similarly, while either IRQI or IRQ2 is processing an interrupt, the output from the AND circuit 29 becomes low level,
While any one of RQI, IRQ2, and IRQ3 is processing an interrupt, the output from the AND circuit 30 is at a low level, so that priority in using the common bus 26 for IRQI to IRQ4 is determined.

Since the circuit of this embodiment is configured with hardware and minimizes software processing, it is possible to reduce the time required to proceed to interrupt processing.

Effects of the Invention Since the interrupt control method of the present invention is configured as detailed above, the interrupt processing is performed on the common bus according to the priority of the interrupt request, the priority order of the interrupt processing is made clear, and the interrupt processing This has the effect of increasing efficiency.

[Brief explanation of the drawing]

Figure 1 is a block diagram of the principle of the present invention, Figure 2 is a circuit diagram of an embodiment of the interrupt control method according to the present invention, Figure 3 is a schematic block diagram of the circuit shown in Figure 2, and Figure 4 is a priority calculation circuit. FIG. 5 shows a block diagram of a conventional interrupt control method. 10.42.43...Processor, 11.26.45...Common bus, 12...Interrupt control unit, 20.21...CPU. 22...Priority calculation circuit, 23.24.27...Latch circuit, 25...Flip-flop, 28-30...ND circuit, 31-33...NOT circuit, 34-37. ...Buffer, 38-41...OR circuit.

Claims (1)

[Claims] In an interrupt control method for controlling interrupt requests for a multiprocessor having a common bus (11) between a plurality of processors (10), the common bus (11) is controlled according to the priority of the plurality of interrupt requests. An interrupt control unit (12) is provided that determines usage priority, and handles interrupt processing based on interrupt requests with high priority.
An interrupt control method characterized in that a common bus (11) is released preferentially.