JPH0449723Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an arbitration circuit for a shared memory accessed by a plurality of microprocessors.

[Prior Art] When multiple microprocessors access memory at the same time, arbitration is performed to determine which microprocessor is allowed to execute based on priority. In conventional shared memory arbitration, arbitration is performed either each time one data is accessed or when a series of data transfers is completed. For example, in the former case, the fourth
As shown in Figure A, after the processor PA accesses the A1 data, there is an access request from the processor PB, and if there is no request from the processor PA at this time, the B2 data is accessed. After that, arbitration is executed, and arbitration is executed every time B3, B4 and one data is accessed, and after the arbitration execution of B4 is completed, when there is an access request from both processors PA and PB, arbitration is executed. Here, an access request for data A5 from processor PA with a high priority is accepted. In the latter case, as shown in Figure 4b, after accessing A1 data from processor PA, the processor
When there is an access request from PB, a series of data transfers is executed from B2 to B6, and even if there is a request from processor PA during this execution, this request is held and the processor transfers data at the end of the series of data transfers up to data B6. Accept access to data A7 from PA.

[Problems to be solved by the invention] In the case shown in FIG. 4a explained above, since arbitration is executed every time one data is accessed, the high-speed access mode of the memory element cannot be used, so the throughput cannot be improved. . In addition, in the case shown in Fig. 4b, the high-speed access mode can be used, but other requests (requests from the processor PA in Fig. 4b) are made to wait until a series of data transfers are completed, which improves the overall throughput. do not.
If the length of data transferred at one time is shortened, the time that other requests are kept waiting will be shortened, but the number of data transfer starts will increase, so even in this case, the overall throughput will not improve. Ta.

[Means for Solving the Problems] The shared memory arbitration circuit according to the present invention allows execution of any one microprocessor by memory access to the shared memory from a plurality of microprocessors, Outputs a memory control signal that executes memory access of the microprocessor by inputting a request confirmation signal that indicates which request from a plurality of microprocessors has been acknowledged, outputs an interrupt enable signal, and displays the completion of one access. When a memory controller that has an access end signal output and multiple memory access request signals are input, even if the access end signal from the memory controller does not indicate completion, if the interrupt enable signal is valid, one of the multiple memory access request signals is input. It has a request confirmation signal that outputs a higher priority request that has been accepted, an arbitration result that outputs lower requests that are not accepted, and an evacuation flag that indicates the existence of an interrupted lower order request, and an evacuation signal. a request arbitration circuit that inputs the arbitration result in response to input of an access completion signal from the memory controller indicating completion of memory access of a request with a higher priority while the flag is displayed; and a request arbitration circuit that temporarily saves the arbitration result from the request arbitration circuit. The present invention is characterized in that it includes an arbitration result save register that outputs to the request arbitration circuit.

[Operation] In a multi-port shared memory, even if it is operating in high-speed access mode in response to a request from one bus, if there is a higher priority request from another bus, the lower priority The operation of the request is interrupted to allow access to the latter request.

[Embodiment] FIG. 1 is a block diagram of an embodiment of the present invention. In FIG. 1, 1 is a memory controller;
2 is a request arbitration circuit, 3 is an arbitration result save register,
4 is an address counter, 5 is an address path, and 6 is a multiplexer. FIG. 2 is a timing chart for explaining the operation of FIG. 1, and FIG. 3 is a state transition diagram of the arbitration circuit of the present invention.

After the A1 data is accessed from the processor PA (not shown), the interrupt enable signal PGEND and the access end signal END are output from the memory controller 1 to the request arbitration circuit 2, and an access request is made from the processor PB (not shown). Assuming that there is no request from the processor PA, the request arbitration circuit 2 outputs the request confirmation signal RF containing the identification signal of the processor PB to the memory controller 1, and outputs the memory control signal MC to execute the memory access of the processor PB. Series of data B2~
Bn allows access in fast mode. At this time, since the memory request RQ was made only from the processor PB, the arbitration result was sent from the request arbitration circuit 2.
AB is for processor PB. In addition,
Addresses are generated by the address counter 4 for a series of data B2 to Bn and output from the multiplexer 6. After that, even if the result confirmed by the above arbitration has been executed and the access end signal END has not been output from memory controller 1, a processor with a higher priority than processor PB
When a memory request RQ is received from PA, the request arbitration circuit 2 confirms that the processor PA has higher priority and outputs a request confirmation signal PF containing an identification signal of the processor PA to the memory controller 1. In memory controller 1, memory control signal MC is used to execute memory access of processor PA.
Output and access data A7. At this time, since the memory access of the lower processor PB has been interrupted, the request arbitration circuit 2 outputs the arbitration result AB (PB) containing the identification signal of the processor PB.
is saved in the arbitration result save register 3, and at the same time, a save flag F is displayed on the request arbitration circuit 2 itself to indicate that the saved request exists. Here, from processor PB to processor PA
Since the processing has been moved to address path 5, if address counter 4 is made to generate an address for data A7, the address for data B will be destroyed. Got the address. Processor PA is data An+1
When the memory access for 1 is completed, the memory controller 1 outputs an access end signal END. On the other hand, the arbitration result from arbitration result save register 3 indicates that the suspended request was PB.
AB(PB)RQ is output, and the request arbitration circuit 2 inputs these and returns (pops) the request from the processor PB. As a result, the request arbitration circuit 2 resets the save flag F and returns to the previous state, resumes access from the interrupted processor PB, and transfers data Bn+1. At this time, address generation is performed by returning to the address counter 4.

[Effects of the invention] As explained in detail above, according to the invention,
Even when operating in high-speed mode, when a request is received from a higher-priority processor, lower-priority operations can be interrupted to allow access to the former request, improving system throughput. can do. Furthermore, since the interrupted lower-level requests are saved, the operation can be restarted immediately without error.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the present invention;
1 is a timing chart for explaining the operation of FIG. 1, FIG. 3 is a state transition diagram of the arbitration circuit of the present invention, and FIGS. 4a and 4b are timing charts for explaining conventional arbitration. 1...Memory controller, 2...Request arbitration circuit, 3...Arbitration result save register, 4...Address counter, 5...Address path, 6...Multiplexer.

Claims (1)

[Claim for Utility Model Registration] In a shared memory arbitration circuit that permits execution of any one microprocessor by memory access to the shared memory from multiple microprocessors, a memory controller having a memory control signal output for executing memory access of the microprocessor in response to input of a request confirmation signal indicating whether the request has been granted, an interrupt enable signal output and an access completion signal output for indicating the completion of one access; When a plurality of memory access request signals are input, even if the access completion signal from the memory controller does not indicate completion, if the interrupt enable signal is valid, the priority order in which the request was acknowledged among the plurality of memory access request signals is The request confirmation signal outputs a higher level request, the arbitration result outputs a lower level request that does not approve the request, and an evacuation flag that indicates the existence of an interrupted lower level request, and while the evacuation flag is displayed, a request arbitration circuit that inputs the arbitration result upon input of an access completion signal from the memory controller indicating completion of memory access for a request with a higher priority; and a request arbitration circuit that temporarily saves the arbitration result from the request arbitration circuit. 1. A shared memory arbitration circuit comprising: an arbitration result save register for outputting to a shared memory arbitration circuit.