JPH01321525A - Hardware semaphore - Google Patents

Abstract

PURPOSE:To avoid such a case where the instructions for updating of different values are simultaneously given to one and the same memory element by provid ing an array of plural memory elements that can be set/reset and a pointer which can set/reset an optional one of these memory elements and controlling the pointer via each process unit. CONSTITUTION:An FF array 1 consists of (n) pieces of FF 11-1n. A reset pointer 2 gives alternately the setting instructions to each FF; while a reset pointer 3 gives alternatively the resetting instructions to each FF respectively. The set and reset timings are instructed to both pointers 2 and 3 via plural process units 41-4n. Both pointers 2 and 3 usually point the different FFs and the number of FFs having the contents '1' is coincident with the number of process units which are carrying out each corresponding job at that time point. Thus the control of parallel jobs is attained by sending the output 10 of the array 1 to a system.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to hardware semaphores, and in particular, in an information processing system consisting of a plurality of processing units 1 to 1 that operate in parallel with each other, it is possible to manage parallel operations between these processing units. Regarding hardware semaphores.

In an information processing system, for example, when multiple processing units are operating in parallel and these units share the same hardware resources, it is possible to perform certain operations at the same time. There may be a limit to the number of processing units that can be executed.

In such a case, keep track of the number of processing units that are executing this specific operation, and if the number of processing units that are executing exceeds the limit, the subsequent specific operation of the processing unit will be delayed. It is necessary to set the state. As this example shows, when designing an information processing system, it is necessary to use the parallel execution status of a specific action 1: by multiple processing units to manage parallel actions among the processing units. Occurs frequently.

Conventionally, as a technology that can be used for this, there is a semaphore (Se + aaphora) as a means of managing parallel programs, which is installed in software. The circuit configuration is as shown in Figure 2.

Referring to FIG. 2, an incrementer 6 and a decrementer 7 are added to the register 5 by one dimension each, and these incrementers 6 and decrementers 7 are controlled by a plurality of processing units 41 to 4n that perform processing operations in parallel with each other. It is configured to do this.

For example, as mentioned above, these multiple processing units
When operating in parallel on a common resource (such as a memory device) that has a limited number of uses, the operating processing units start the incrementer 6 and set the initial f/f.

The processing unit that has completed its operation activates the decrementer 7 to control the content of the register 5 to be incremented by -1. By doing this,
The number of processing units currently using a common resource can be determined by the contents 10 of this register 5. Therefore, for processing units exceeding the usage limit of the resource,
It also becomes possible to perform management control such that resources are put on standby.

However, in the direct realization of parallel program management means in the design of such software, an incrementer and a decrementer are added to the same register, and therefore a signal for increment and a signal for decrement are used. However, there are disadvantages in that the processing becomes complicated when the signals arrive consecutively for different periods of time, and the overall hardware requirements increase.

SUMMARY OF THE INVENTION Therefore, the present invention has been made to solve the above-mentioned drawbacks of the previous R. It is in.

According to the present invention, in an information processing system consisting of a plurality of processing units that operate in parallel with each other, there is provided a hardware semaphore for managing parallel operations between these processing units, each of which has a set of The processing unit includes a plurality of resettable storage elements, set pointer means for alternatively specifying a set of these storage elements, and reset pointer means for alternatively specifying reset of the storage elements, setting a storage element designated by the set pointer means in response to the start of its own processing operation;
Further, in response to the completion of its own processing operation of the processing unit, the storage element specified by the reset pointer means is reset, and the parallel operation between the processing units is controlled by the contents of the storage element. A hardware semaphore characterized by being managed is obtained.

Example The present invention will be described in detail below using the drawings.

FIG. 1 is a block diagram of an embodiment of the invention.

F consisting of n FFs (flip-flops) 11 to 1n
An F array 1 is provided, and there are a set pointer 2 that selectively sets each FF, and a reset pointer 3 that selectively instructs to reset each FF. Set and reset timings are instructed by the processing units 41 to 4n.

These plurality of processing units 41 to 4n are units capable of parallel operation that share and use resources in which the number of units that can simultaneously execute a specific operation is limited. Each unit generates a command signal to set (1) the FF pointed to by the set pointer 2 when starting the specific operation. When this set is made, the set pointer 2 immediately points to another FF whose contents are in the reset (0) state for the next set.

Further, when each unit finishes the specific operation, it generates a command signal to reset the FF pointed to by the reset pointer 3. When this reset is performed, the reset pointer 3 indicates the FF to be reset next, that is, the FF set by the processing unit that will next finish the specific operation.

Both pointers 2 and 3 usually point to different FFs,
The number of FFs whose content is 1 represents the number of processing units that are performing the specific operation at that time, so if the output 10 of this FF array 1 is sent to the system, it will be possible to perform parallel operations. Management becomes possible. For example, when the number of FFs in this set is less than or equal to a predetermined value (for example, the number of processing units that can use a common resource simultaneously), the FFs pointed to by cellar 1 to pointer 2 are transferred to cellar 1.
By doing so, each processing unit can start the specific operation.

In particular, if the contents of all FT.'' are in the reset (0) state, it means that there is no equivalent processing unit executing the specific operation.Only in this case, both pointers 2 and 3 are the same. However, in other cases, both pointers will not point to the same FF.

The instruction content of the reset pointer 3 does not necessarily have to be immediately after finishing the particular operation; it is sufficient that the FF set when a certain processing unit starts the operation can be reset when the operation is finished.

In the above embodiment, I? F' is used to set and reset the contents of 1.0, but 1.0
It is also possible to use other storage elements that can take on values other than .

The present invention is applicable not only to cases where units capable of parallel operation share resources that limit the number of units that can execute a specific operation simultaneously, as shown in the embodiments, but also when all other units This can generally be used when the parallel execution status of a particular operation needs to be used to manage parallel operations between processing units, such as when another operation can only be started when one operation is not being performed.

According to the present invention, an array of a plurality of memory elements that can be set and reset is used, and a pointer that can set and reset any one of these memory elements is provided so that each memory element can be set and reset. Since these pointers are controlled by the processing unit, it is possible to prevent simultaneous update instructions for different values to the same storage element, and it is possible to prevent complicated control and increase in complicated hardware. It has the effect of becoming.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a diagram showing an example of a conventional hardware semaphore. Explanation of codes of main parts 1...FF array 2...Cera 1 to pointer 3...Reset pointer 11 to l rL...FF

Claims (1)

[Claims] (1) In an information processing system consisting of a plurality of processing units that operate in parallel with each other, a hardware semaphore that manages parallel operations between these processing units, and a plurality of memory elements each of which can be set and reset. , including set pointer means for alternatively specifying a set of these storage elements, and reset pointer means for alternatively specifying a reset of the storage elements, and responsive to the start of its own processing operation of the processing unit. and sets the memory element designated by the set pointer means, and resets the memory element designated by the reset pointer means in response to completion of its own processing operation of the processing unit, and the memory element designated by the reset pointer means is reset. A hardware semaphore characterized in that parallel operations between the processing units are managed based on set/reset contents of a storage element.