JPH01233532A - Trace control system in multi-processor system - Google Patents

Abstract

PURPOSE:To quickly analyze a fault and to improve the reliability by outputting stored data of a trace buffer in case of a dump output at the time when a fault has been generated. CONSTITUTION:A trace buffer 5 for storing the data for detecting an interruption is provided in a system control processor 2, and in case of a dump output at the time when a fault has been generated, the stored data of the trace buffer 5 is outputted. In such a way, a fault analysis can be executed without executing newly a reproducing test, and the fault can be settled in an early state.

Description

[Detailed Description of the Invention] [Summary] In a multiprocessor system comprising a plurality of instruction control processors (hereinafter abbreviated as IPU), one system control processor (hereinafter abbreviated as SPU), a main storage device, and an input/output device. Regarding the trace control method for tracking failures when they occur, the aim is to quickly analyze failures, quickly implement responses and countermeasures for failures, and thereby obtain a highly reliable system. In a trace control method in a multiprocessor system that includes an IPU that controls multiple instructions, one SPU that controls the entire system, a main storage device, and an input/output device, interrupt detection is performed in the SPU. A trace buffer (hereinafter abbreviated as TB) for storing data at the time of failure is provided, and when a dump is output when a failure occurs, the data stored in the TB is output and the failure analysis is performed quickly.

[Industrial application field]

The present invention includes multiple IPUs, one 5PtJ, main memory,
The present invention also relates to a trace control method for tracing failures when they occur in multiprocessor systems equipped with input/output devices.

[Conventional technology]

When a failure occurs in a multiprocessor system consisting of multiple IPUs, SPUs, main storage devices, and input/output devices (■0) as shown in Figure 2, trace information is used as one means of failure analysis. is used.

Conventionally, as a means for collecting trace information, an additional device for tracing is attached, a tracing program is added, and failure analysis is performed through reproduction tests. FIG. 7 shows a conventional failure analysis procedure.

[Problem to be solved by the invention]

In the current situation as described above, there are many problems such as requiring a large amount of time to analyze a fault, or applying an additional device and trace program to the fault, which makes it impossible to identify the cause (for example, a fault that occurs due to timing). There are issues to be solved.

An object of the present invention is to provide a highly reliable system in which failure analysis can be performed quickly and failure-related responses and countermeasures can be quickly realized.

[Means to solve the problem]

In the present invention, as illustrated in FIG.
In a trace control method for a multiprocessor system, the 5PIJ2 is provided with a TBS for storing data at the time of interrupt detection, and when outputting a dump when a failure occurs, the data stored in the TB5 is output and the failure analysis is performed. A trace control method in a multiprocessor system is provided that is characterized by rapid execution.

[For production]

As described above, in the present invention, TB5 is provided in SPU 2, traces the interrupt timing from IPU 1,
Data is stored in TB5, and trace information is extracted by the dump function of the failure analysis means when a failure occurs. This allows failure analysis to be performed without conducting new reproduction tests, and enables early resolution of failures.

〔Example〕

A trace control method in a multiprocessor system as an embodiment of the present invention will be explained with reference to FIGS. 1, 3, 4, 5, and 6.

As shown in FIG. 1, the system of this embodiment includes a plurality of (three) IPU 1 and SPU 2 having TBS.
, a main storage device 3, and a plurality of input/output devices 4.

The IPUI, 5PU2, and main storage device 3 are connected by a bus, and the input/output device 4 is connected to 5Ptl2.

Interrupt signals from multiple IP[I 1 to SPU 2 are aggregated into one signal, and the logical OR is calculated to generate SP[I 2
Since the IPU interrupts to SPU 2 are notified to SPU 2, they are not controlled in parallel.

FIG. 3 shows a flowchart showing the failure analysis procedure of the embodiment. That is, when a failure occurs, memory dump processing is first performed. Here, dumping refers to transferring part or all of the contents of one part of a storage device to another part by a program. Next, a failure notification is issued,
The IPU number and execution command of the data read from TB5 are analyzed (memory dump analysis step). If the cause cannot be determined by this, the process branches and the cause is analyzed separately. When the cause is identified, appropriate measures will be taken.

FIG. 4 shows a flowchart of the trace data storage process in the interrupt processing of the embodiment. First, when an interrupt is issued from the IPU, interrupt processing is executed, and then, as additional logic, an IPU number and IPU control information are set into the area of TB5. Thereafter, the process proceeds to execution of the request process.

FIG. 5 exemplifies the format of data storage in TB5. When an IPU interrupts, store the IPU number and ['U control information in the buffer according to the trace buffer pointer address, compare whether the trace buffer address is final, and when the trace buffer address is final, set the first trace buffer address to the trace buffer pointer address. Insert (A).

By passing through the additional logic shown in FIG. 4, it is possible to determine which IPU has performed what processing in terms of timing.

FIG. 6 shows a flowchart of dump processing when a failure occurs. In this process, the dump flow when a failure occurs is T
Logic is added to dump the B area data from (S) to (B) shown in FIG. The process zero control memory dump step in FIG. 6 is a step for displaying on a display device or the like.

As mentioned above, by providing the additional logic shown in FIGS. 4 and 6, the failure analysis procedure of the embodiment of FIG. 3 can be implemented.

〔Effect of the invention〕

According to the present invention, a trace buffer can be dumped and a fault can be analyzed quickly, and countermeasures and countermeasures can be taken quickly, thereby making it possible to obtain a highly reliable multiprocessor system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of the present invention, FIG. 2 is a block diagram of a multiprocessor system to which the present invention is applied, FIG. 3 is a diagram showing a failure analysis procedure in an embodiment of the present invention, and FIG. is a flowchart of trace data storage processing for interrupt processing in the embodiment, FIG. 5 is a diagram showing the storage format of the trace buffer in the embodiment, FIG. 6 is a flowchart of dump processing in the event of a failure in the embodiment, and FIG. It is a flowchart which shows the failure analysis procedure of a conventional example. In the figure, 1...IPU, 2...SPU. 3... Main storage device, 4... Input/output device, 5.
・TBo

Claims (1)

[Claims] A multiprocessor that includes an instruction control processor (1) that controls multiple instructions, one system control processor (2) that controls the entire system, a main storage device (3), and an input/output device (4). In the trace control method in the system, a trace buffer (5) is provided in the system control processor (2) to store data at the time of interrupt detection, and when outputting a dump when a failure occurs, the data stored in the trace buffer (5) is A trace control method for multiprocessor systems that outputs and quickly performs failure analysis.