JPS60100230A - Real-time inspecting device for main storage part - Google Patents

Abstract

PURPOSE:To prevent a runaway and improve reliability by inspecting the contents of a main storage part at the timing when a main CPU to be inspected releases a bus. CONSTITUTION:A main computer system 13 and a real-time main storage part inspecting device 4 are connected together through a bus 3 which transfers a data signal 31, address signal 32 in a main storage part 1, and status signal 33. This inspecting device 4 consists of an inspecting CPU 7, etc., and inspects whether data stored in an inspection storage part 12 coincide with the contents of the main storage part 1 or not. When this inspection is performed, the main CPU 2 reads instructions out of the main storage part 1 at time t1-t2 and decodes those instructions at time t2-t3, but the main CPU 2 releases said bus 3 at this time and said inspecting device 4 occupies said bus 3 at time t5-t6 with an operation signal 8 detected by a bus monitor part 5 to store the data from a main storage part 1 in the inspection storage part 12 and perform the inspection.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field to which the Invention Pertains] The present invention relates to a real-time main memory inspection device, particularly a real-time main memory inspection device for inspecting a main memory in which instructions are stored while a computer is operating. This invention relates to a main storage inspection device.

[Common technology]

In general, in a sequential processing type digital converter that reads instructions from the main memory where the instructions are stored, decodes and executes them, the instruction code stored in the main memory may be affected by disturbance noise, etc. If it is destroyed due to any cause,
Since the computer may run out of control and, in some cases, lead to extremely dangerous results, it is necessary to provide some kind of protection.

[Prior art]

In conventional sequential processing digital computers, the watchdog method, in which a hard timer is executed to reset a task at fixed time intervals, and a runaway is detected when the task is not executed, and the inspection computer system are Separately from the computer system, a method has been implemented in which both converters are connected via a communication line, and the inspection computer monitors the main computer via the communication line.

However, none of these methods directly inspects the main memory where instructions are stored, but instead attempts to detect runaway in the upper converter. It's not something you do.

Furthermore, these testing methods omit part of the instruction execution time of the computer to perform the testing, which reduces the utilization rate of the computer and, in systems that require higher-speed processing, A problem arises in that it is a non-destructive inspection method.

Further, a specific area may be provided in the main memory, for example,
Although methods such as providing parity bits have been implemented,
Since a redundant area is provided in the main memory, the usage rate of the main memory decreases and there are problems in terms of economy.

In other words, the conventional method of testing the main memory section has the disadvantage that runaway cannot be prevented and reliability is low.

[Purpose of the invention]

[Structure of the Invention] The real-time main memory inspection device of the present invention includes a sequential processing type digital main computer that reads, decodes, and executes instructions in one cycle, and a main memory that stores OIJ instructions. In a real-time main memory inspection device connected to the bus for computer systems connected to each other via a path, a bus monitor unit detects the instruction decoding time of the main computer;・1
*A control unit that occupies the bus during the time of decoding the issued command and reads out the contents of the main memory as data independently of the main computer, and a test storage unit that temporarily stores the read data. and a test CPU unit that confirms that the stored content of the test storage unit and the pre-stored content of the main storage unit are the same data.

[Explanation of Examples]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram including an embodiment of the present invention. A main memory section 1 stores poem commands, and a main CTJ U2 is a sequential processing type main central processing unit that executes this command.

A main computer system controller connected via a dox 3 that transfers a data signal 31, an address signal 32 specifying a specific address in the main memory 1, and a status signal 33 representing the operational axis of the main C)'U2. 4 is connected.

This real-time main memory inspection device 4 includes a bus monitor section 5, a control section 6, a test CPU section 7, and a test storage section 12.
Contains. The bus monitor section 5 decodes the status signal 33 of the path 3, detects the start and end of the instruction decoding time of the upper CPU 2, and informs the control section 6 and the controller 5 that the upper CT' U 2 is decoding the instruction. Inspection C
The PU unit 7 is notified by the operation signal 8 and the operation signal 9. When the control unit 6 learns from the 1 operation signal 8 from the bus monitor unit 5 that the upper CPU 2 is decoding an instruction in the main memory unit 1, it sends an address signal 32 indicating the portion of the main memory unit 1 to be inspected. The content of the main memory section 1 corresponding to the address is read as data by the data signal 31 and is temporarily stored in the test memory section 12, and at the same time, the above-mentioned data is sent to the test CPU section 7 by the operation signal lO. ′
i8: Report that the loading work has been completed. Test storage section 1
2 is where the data signal 31 on the bus 3 read from the main storage section 1 is stored as data by the control section 6, and accessed by the inspection CT'U section 7 and stored on the internal bus 11. The accumulated data is sent to the inspection CPU section 7 via the inspection CPU section 7. When the test CPU section 7 learns from the operation signal 10 that the necessary data has been stored in the test storage section 12, it reads out the data stored in the test storage section 12 via the internal bus 11, and combines the data with the data stored in the test storage section 12 in advance. It is checked whether the contents are the same as the contents of the address stored in the main storage section 1. This test result is the same.
One task (No. 8 33) is sent.

Next, the time relationship between the operations of the main CPU 2 and the real-time main storage testing device 4 will be explained with reference to the timing diagram shown in FIG.

The operation timing Illa shown in FIG. 2 is at time 1+ in the operation time chart of main CP [J2 in FIG. 1.

The period t2 is the instruction reading time of the main CPU 2, time tz.

t3 is the instruction decoding time, time t3. The period t4 is the instruction execution time, and the bus timing Tb actually reads one instruction code to be checked from the main memory 1.

Next, the operation will be explained.

Before starting the test, all correct instruction codes stored in the main storage section 1 are transferred to the test storage section 12. Main CT
'[J2 reads instructions from main memory 1 between time t1 and t2, and decodes the instructions read between time t2 and t3. At this time, main CP[J2 releases bus 3, so The time main memory inspection device 4 occupies the bus 3 from time t6 to t6 based on the operation signal 8 detected by the bus monitor 5, and reads one instruction code from the main memory 1 from time ts to 16. In the meantime, the data is read and temporarily stored in the test storage unit 12. After that, the inspection CP [J part 7 releases the occupied bus 3, reads this stored data and the data at the same address in the same data stored in the main memory part 1 stored in advance, and compares it to the internal bus 11 to see if they match. If they match, it is sent to the control unit CPU2.

〔Effect of the invention〕

The real-time main memory inspection device of the present invention can inspect the contents of the main memory while the main CPU is operating by capturing the timing when the main CPU to be inspected releases the bus. Since runaway caused by changes due to noise or the like can be prevented, this has the great effect of improving the reliability of the computer system.

[Brief explanation of drawings]

FIG. 1 is a block diagram including an embodiment of the present invention, and FIG. 2 is a timing diagram showing the timing in the embodiment shown in FIG. 1... Main memory section, 2... Main CPU, 3.
River...bus, A,,,,,, Nakanakama Juukon Haruka Haruta Soakuri 1 Go h signal, 32...address signal,
33...Status signal, 13...+
Computer system, death... bus monitor department, 6
...Control section, 7... mark/inspection CPU section, 8. 9. 10...Movement, 11...
・Internal bus, 12...Test storage section, Ta...
...Operation timing, Tb...Bus occupancy 3
J'y7 Zuken? figure

Claims (1)

[Claims] A serial processing type digital main computer in which reading, decoding, and executing an instruction constitutes one cycle and a main memory section in which the instruction is stored are connected to each other via a bus. The real-time main memory inspection device includes a bus monitor section that detects the instruction decoding time of the main computer, and a bus monitor section that occupies the bus during the instruction decoding time detected by the bus monitor section and is independent of the main computer. a control section that reads out the contents as data from the main storage section; a test storage section that temporarily stores the read data; and a control section that reads out the contents as data from the main storage section; a test storage section that temporarily stores the read data; Inspection CPU that confirms that the content is the same data.
1. A real-time main memory inspection device comprising: