JP2638014B2 - Signal detection circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a signal detection circuit in a digital electronic circuit.

[Prior Art] Conventionally, this kind of signal detection circuit is composed of a monostable multivibrator 11, an external capacitor 12, and a resistor 13, as shown in a circuit example shown in FIG. If the rise of the signal under test a does not change during the time determined by the time constant of the resistor 13, the output of the monostable multivibrator 11 cannot be maintained at "1" level and becomes "0". Was to be detected.

[Problems to be Solved] The conventional signal detection route described above has the following problems.

Since the detection time is determined by the time constants of the capacitor and the resistor, these elements are required to have high accuracy and are expensive.

It is difficult to detect if the signal under measurement does not have a fixed period.

The inclusion of capacitors and resistors makes integration difficult and bulky.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and does not use passive components such as capacitors and resistors and integrates only digital circuits that can be easily integrated. It is an object of the present invention to provide a signal detection circuit capable of easily and reliably detecting a non-constant signal to be measured.

[Means for Solving the Problems] In order to achieve the above object, a signal detection circuit according to the present invention includes a selector for selecting and outputting either a signal fixed to 1 or 0 level, and a selector for connecting the selector to a data terminal. And a processor for inverting the data input of the flip-flop, and for detecting the presence or absence of the signal to be measured based on the output of the flip-flop. There is a configuration.

That is, "0" and "1" are put into a set of 2-1 data selectors, respectively, and either one of the data is selected by a processor command. When the rising edge of the signal to be measured is input to the clock terminal of the data flip-flop provided at the subsequent stage of the selector, the information of the selector is taken into the data flip-flop.

Thereafter, the processor reads the contents of the port of the data flip-flop, and if the contents match the contents selected by the processor earlier, the signal under measurement is operating and does not match. If not, it is determined that it is not operating.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

In the drawing, reference numeral 1 denotes a selector for selecting and outputting either a signal fixed to a “1” or “0” level.
Reference numeral 2 denotes a data flip-flop, which inputs a signal output from the selector 1 to a data terminal 2a, and a clock terminal.
The measured signal a is input to 2b.

3 is a 3-state buffer, and 4 is a processor.
The three-state buffer 3 includes a data flip-flop 2
Functions as a port for causing the processor 4 to read the contents of The processor 4 reads the data of the data flip-flop 2 via the data bus.

Reference numeral 6 denotes a data flip-flop for setting a signal, which sets a value “0” or “1” output from the address decoder 5 by the processor 4.

 Next, the operation will be described.

The processor 4 accesses the data flip-flop 6 through the address decoder 5 and sets the value output from the data bus of the processor 4 to the data flip-flop 6. At this time, if “0” is output from the data bus of the processor 4, “0” is output to the data flip-flop 6.
Is set, and as a result, the selector 1 selects “0”.

Conversely, if "1" is output to the data bus of the processor 4, the selector 1 selects "1".

Thereafter, when the signal to be measured is input to the signal terminal 7, the data flip-flop 2 takes in the data of the selector 1 at the rise of the signal. Then, the data of the data flip-flop 2 sent to the data bus is read by the processor 4 and the contents written in the data flip-flop 6 are compared. As a result, in the processor 4, the signal terminal 7
Operation is confirmed.

Although a processor is used in the present invention, since the processing of this circuit is not a time-consuming processing, it is usually possible to perform other tasks and perform the processing of this circuit at regular intervals. However, the use of a processor is not a disadvantage.

[Effects of the Invention] As described above, according to the present invention, a circuit can be constituted only by a digital circuit without using passive components such as a capacitor and a resistor. This has the effect that the program can be reliably dealt with by extending the cycle by changing the program.

[Brief description of the drawings]

FIG. 1 is a block diagram of a signal detection circuit according to one embodiment of the present invention, and FIG. 2 is a configuration diagram of a conventional signal detection circuit. 1: Selector 2: Data flip-flop 3: 3-state buffer 4: Processor (CPU) 5: Address decoder 6: Data flip-flop (DF) 7: Signal input terminal

Claims (1)

(57) [Claims] 1. A selector for selecting and outputting either a signal fixed to 1 or 0 level, and a flip-flop for inputting an output signal of the selector to a data terminal and inputting a signal to be measured to a clock terminal. And a processor for inverting the data input of the flip-flop, and detecting the presence or absence of the signal under measurement based on the output of the flip-flop.