JP3186449B2 - Interrupt source register circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt factor register circuit, and more particularly to a method for detecting an asynchronous interrupt factor incorporated in an LSI (Large Scale Integrated Circuit).

[0002]

2. Description of the Related Art Conventionally, in this type of interrupt factor detection method, as shown in FIGS.
When INT7 occurs (step S11 in FIG. 5) and the interrupt factors of the respective interrupts INT0 to INT7 are held in the interrupt factor registers (RS-LATCH) 10-0 to 10-7, respectively, the OR circuit 11 Then, an interrupt notification is output to a host device (not shown).

When the host device receives the interrupt notification, it outputs an I / O read signal to the interrupt factor registers 10-0 to 10-7, and outputs the I / O read signal to the interrupt factor registers 10-0 to 10-7 via the I / O data bus 100. By reading the content of 10-7 (step S12 in FIG. 5), the interrupt factor is recognized.

[0004] In addition, the host device determines whether the interrupt factor register 10-
When the I / O read operation is completed after reading all the contents of 0 to 10-7, a reset signal RESET is output to each of the interrupt factor registers 10-0 to 10-7, and the interrupt factor register 10 is output.
-0 to 10-7 are uniformly reset (step S13 in FIG. 5).

That is, the higher-level device is provided with the interrupt factor register 10
When all of the contents of −0 to 10−7 are read, the address is directly specified from the higher-level device to the interrupt cause registers 10-0 to 10−7, whereby the interrupt cause registers 10−0 to 10−1 are designated.
The contents of 0-7 are reset.

[0006] The higher-level device is provided with interrupt factor registers 10-0 to 1
When the contents of 0-7 are reset, the occurrence of an interrupt is detected again.

[0007]

In the above-described conventional method for detecting an interrupt factor, the content of the interrupt factor register is reset after the completion of the I / O read from the interrupt factor register. If an interrupt occurs at the same time as the end of I / O read when detecting an unknown interrupt cause of the asynchronous system, the contents of all the interrupt cause registers are reset. become unable.

When the contents of the interrupt cause register are reset by address designation by the host device, the resetting of the contents of the interrupt cause register is controlled by software, so that complicated processing is executed in the host device. If this is the case, the burden on the host device will increase.

Therefore, an object of the present invention is to solve the above-mentioned problems, to reset only an interrupt factor register holding an interrupt factor, and to recognize an interrupt that has occurred later, and An object of the present invention is to provide an interrupt factor register circuit capable of reducing a load.

[0010]

An interrupt factor register circuit according to the present invention comprises a holding means for holding an interrupt factor, and an interrupt factor which is a content held by the holding means in response to a read start timing by a read signal. And a reset means for resetting the content held by the holding means when the interrupt factor is latched by the latch means and a read end timing by the read signal is detected. And the interrupt factor is
Latched by the latch means and the read signal is input
A reset circuit that is set when the resetting circuit is set, and the holding means is provided only during a period in which the read end timing by the read signal is detected and the reset circuit is set.
The reset circuit is reset.

According to another aspect of the present invention, there is provided another interrupt factor register circuit which includes a plurality of holding means for holding respective interrupt factors, and which is provided corresponding to each of the plurality of holding means and responds to a read start timing by a read signal. A plurality of latch means for latching an interrupt factor which is a content held by the plurality of holding means, and a plurality of latch means provided corresponding to each of the plurality of holding means, and wherein the interrupt factor is latched by the latch means. And a plurality of reset means for resetting the contents held by the holding means when a read end timing by the read signal is detected, provided in correspondence with each of the plurality of holding means. and a plurality of detecting means for detecting the read end timing of the read signal, provided corresponding to said plurality of holding means each, the interrupt factor Or latched in said latch means
A plurality of sets which are set when the read signal is input.
A reset circuit, wherein the holding means and the reset circuit are provided only during a period in which read end timing by the read signal is detected and the reset circuit is set.
And reset it.

Another interrupt factor register circuit according to the present invention is provided with a plurality of holding means each for holding an interrupt factor, and provided in correspondence with each of the plurality of holding means and responsive to a read start timing by a read signal. A plurality of latch means for latching an interrupt factor which is a content held by the plurality of holding means, and a plurality of latch means provided corresponding to each of the plurality of holding means, and wherein the interrupt factor is latched by the latch means. A plurality of reset means for resetting the contents held by the holding means when a read end timing by the read signal is detected, provided in common with each of the plurality of holding means; Detection for detecting the read end timing by the read signal
Means , provided corresponding to each of the plurality of holding means ,
The interrupt factor is latched by the latch means and the
Multiple resets that are set when an output signal is input
A reset circuit for resetting the holding means and the reset circuit only during a period when the read end timing based on the read signal is detected and the reset circuit is set.

[0013]

When the contents of an interrupt factor register are latched in a latch circuit in response to an I / O read signal from a higher-level device, and when the interrupt factor is latched in the latch circuit and an I / O read signal is input, The interrupt factor register reset circuit.

When the rise detection circuit detects the end of the I / O read operation, a reset signal from the interrupt factor register reset circuit is output to the interrupt factor register and the interrupt factor register reset circuit via an AND circuit. I do.

This makes it possible to reset only the interrupt factor register holding the interrupt factor, and to recognize an interrupt that has occurred later. In addition, by resetting the interrupt factor register holding the interrupt factor in a self-excited manner, the burden on the host device can be reduced.

[0016]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. Referring to the figure, an interrupt factor register circuit according to an embodiment of the present invention includes registers 1-i (i = 0 to 7), each of which is an interrupt factor register (RS-LATCH) 2-. i and a latch circuit (D-
LATCH) 3-i, an interrupt factor register reset circuit 4-i, a rise detection circuit 5-i, and an AND circuit 6-i
It consists of

In FIG. 1, interrupt factor register 2-0 of register 1-0, latch circuit 3-0, interrupt factor register reset circuit 4-0, rise detection circuit 5-0, and AND circuit 6-0 Only one is shown.

Register 1-i Each interrupt factor register 2
-I are the NOR circuits 2a-i and 2b-i (the NOR circuits 2a-1
2a-7 and 2b-1 to 2b-7 are not shown) and are connected to corresponding interrupt factor sources.

When an interrupt INT0-INT7 from the source of the interrupt factor is input, the interrupt factor register 2-i holds the interrupt factor and outputs the interrupt factor to the latch circuit 3-i. I do.

The latch circuit 3-i has an interrupt factor register 2-
When an interrupt factor is input from i, the interrupt factor is output to the OR circuit 7. When an I / O read signal IORD is input from a higher-level device (not shown), the latch circuit 3-i latches the contents of the interrupt factor register 2-i in response to the I / O read signal IORD. At the same time, the contents are output onto the I / O data bus 100.

Further, the latch circuit 3-i stores the interrupt factor register 2 latched in response to the I / O read signal IORD.
The contents of -i are output to the interrupt factor register reset circuit 4-i.

The interrupt factor register reset circuit 4-i includes AND circuits 4a-i (AND circuits 4a-1 to 4a-7 are not shown) and NOR circuits 4bi and 4ci (NO circuit 4b).
-1 to 4b-7 and 4c-1 to 4c-7 are not shown).

In the interrupt factor register reset circuit 4-i, the latch circuit 3-i latches the interrupt factor held in the interrupt factor register 2-i, and the I / O read signal IORD is input from the host device. Sometimes set, AND circuit 6
Output "1" to -i.

The rising edge detection circuit 5-i receives I from the host device.
When detecting the rising of the / O read signal IORD, it outputs "1" to the AND circuit 6-i. When "1" is input from the interrupt factor register reset circuit 4-i and the rising edge detection circuit 5-i, the AND circuit 6-i outputs a reset signal to the interrupt factor register 2-i and the interrupt factor register reset circuit 4. Output to -i.

In the above-described interrupt factor register circuit, each of the registers 1-i is configured to detect one interrupt factor. In FIG. 1, the interrupt factor register circuit includes eight registers 1-i. With this configuration, it is possible to recognize an interrupt factor for one byte.

FIG. 2 is a flowchart showing the operation of one embodiment of the present invention. The operation of the embodiment of the present invention will be described with reference to FIGS.

Each register 1-i stores interrupts INT0 to IN
The interrupt input is detected until T7 is generated (step S1 in FIG. 2). When the interrupts INT0 to INT7 are generated, the occurrence of the interrupt is notified to the host device via the OR circuit 7.

When the host device receives the notification of the occurrence of the interrupt,
An I / O read signal IORD is output to read the contents of the interrupt factor register 2-i of each register 1-i. Each register 1-i is provided with an I / O read signal IOR from a higher-level device.
When D is input (step S2 in FIG. 2), the contents of the interrupt factor register 2-i are latched in the latch circuit 3-i (step S3 in FIG. 2).

When the I / O read signal IORD is input from the host device, the interrupt factor register reset circuit 4-i determines whether or not its own register is a register to which the interrupts INT0 to INT7 have been input (FIG. 2). Step S4).

When the interrupt factor register reset circuit 4-i determines that its own register is a register to which the interrupts INT0 to INT7 have been input, it is set to a state of outputting a reset signal (step S5 in FIG. 2), and the AND circuit 6 −i
Is output as "1".

The interrupt factor register reset circuit 4-
If i determines that its own register is not a register to which the interrupts INT0 to INT7 have been input, it is not set to a state for outputting a reset signal. Therefore, the register 1-i
Returns to the process of detecting the input of the interrupts INT0 to INT7.

Thereafter, the rise detecting circuit 5-i terminates the I / O read by the host device, that is, the I / O read signal I
When detecting the rise of ORD, "1" is output to the AND circuit 6-i.

As a result, the AND circuit 6-i has the interrupt factor register reset circuit 4-i and the rise detection circuit 5
Since "1" is input from -i, a reset signal is output to the interrupt factor register 2-i and the interrupt factor register reset circuit 4-i, and each is reset (step S6 in FIG. 2).

Even if an interrupt occurs to another register during the I / O read by the host device, the interrupt factor register reset circuit 4-i uses the register whose own register holds the interrupt factor. It is set when it is determined that the I / O read signal is present and the I / O read signal IORD is input, so that the interrupt factor generated during the I / O read by the host device is not reset.

The cause of the interrupt generated during the I / O read is reset when the I / O read signal IORD is received from the host device by the next interrupt notification.

FIG. 3 is a block diagram showing the configuration of another embodiment of the present invention. In the figure, in another embodiment of the present invention, the rise detection circuit 9 is connected to each of the registers 8-j (j = 0, 1, 2, 2).
The configuration is the same as that of the embodiment of the present invention except for the common use between 3), and the same components are denoted by the same reference numerals. The operation of the same component is the same as the operation of the embodiment of the present invention.

In another embodiment of the present invention, the rise detecting circuit 9
Is shared among the registers 8-j, thereby reducing the circuit scale. In another embodiment of the present invention, four interrupt factors can be recognized.

As described above, the contents of the interrupt factor register 2-i are latched by the latch circuit 3-i in response to the I / O read signal IORD from the host device, and the latch circuit 3-i is latched.
Is latched in the rising edge detection circuit 5-i, 9
Detects the end of the read operation by the I / O read signal IORD, the interrupt factor register reset circuit 4-i
And, by resetting the contents of the interrupt factor register 2-i by the AND circuit 6-i, only the interrupt factor register 2-i holding the interrupt factor is reset, and the interrupt generated later is recognized. be able to.

Further, when the interrupts INT0 to INT7 are generated, the interrupt factor register 2-i holding the interrupt factors is reset in a self-excited manner, so that the burden on the host device can be reduced. Furthermore, the addresses can be used effectively by collecting the asynchronous interrupt factor registers 2-i.

[0041]

As described above, according to the present invention, the contents of a plurality of holding means each holding an interrupt factor are latched by the corresponding latch means in response to an I / O read signal from a higher-level device. , The interrupt factor is latched by the latch means and I
By resetting the contents of the holding means when the end of the read operation by the / O read signal is detected, it is possible to reset only the holding means holding the interrupt factor and recognize the interrupt generated later. Thus, there is an effect that the burden on the host device can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a flowchart showing the operation of one embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of another embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a conventional example.

FIG. 5 is a flowchart showing the operation of the conventional example.

[Explanation of symbols]

 1-0 to 1-7, 8-0 to 8-3 Register 2-0 Interrupt cause register 2a-0, 2b-0, 4b-0, 4c-0 NOR circuit 3-0 Latch circuit 4-0 Interrupt Cause register reset circuit 5-0,9 Rise detection circuit 4a-0,6-0 AND circuit 7 OR circuit

Claims (3)

(57) [Claims] A holding means for holding an interrupt factor; a latch means for latching an interrupt factor which is a content held by the holding means in response to a read start timing by a read signal; a interrupt factor register circuit and means for resetting the contents held in the holding means when the read end timing according to the latched and the read signal is detected to the means, the interrupt factor is the
Latched by the latch means and the read signal is input
A reset circuit that is set when the resetting circuit is set, and the holding means is provided only during a period in which the read end timing by the read signal is detected and the reset circuit is set.
Interrupt factor register circuit and wherein the forming so as to reset and the reset circuit. 2. A plurality of holding units each holding an interrupt factor, and a plurality of holding units provided corresponding to each of the plurality of holding units, the contents held by the plurality of holding units in response to a read start timing by a read signal. A plurality of latch means for latching a certain interrupt factor, and a read end timing detected by the read signal detected when the interrupt factor is provided in correspondence with each of the plurality of holding means and the latch means is latched by the latch means An interrupt factor register circuit including a plurality of reset means for resetting the content held by the holding means when the reading is performed, wherein the interrupt factor register circuit is provided corresponding to each of the plurality of holding means and detects a read end timing by the read signal. And a plurality of detecting means provided for each of the plurality of holding means , and the interrupt factor is latched to the latch means.
Touched and set when the read signal is input.
A plurality of reset circuits, wherein the holding means and the reset circuit are only provided during a period when the read end timing based on the read signal is detected and the reset circuit is set.
And a reset circuit for resetting the reset circuit. 3. A plurality of holding means each holding an interrupt factor, and a plurality of holding means provided corresponding to each of the plurality of holding means and held by the plurality of holding means in response to a read start timing by a read signal. A plurality of latch means for latching a certain interrupt factor, and a read end timing detected by the read signal detected when the interrupt factor is provided in correspondence with each of the plurality of holding means and the latch means is latched by the latch means An interrupt factor register circuit including a plurality of reset means for resetting the content held by the holding means when the reading is performed, wherein the interrupt factor register circuit is provided in common with each of the plurality of holding means and detects a read end timing by the read signal A detecting unit provided for each of the plurality of holding units , wherein the interrupt factor is latched by the latch unit;
A plurality of sets which are set when the read signal is input.
A reset circuit, wherein the holding means and the reset circuit are provided only during a period in which read end timing by the read signal is detected and the reset circuit is set.
And an interrupt factor register circuit.