JP2001154908A - Memory interface - Google Patents

Abstract

PROBLEM TO BE SOLVED: To read data from a memory without stopping the main operation of processing the data and writing the result to the memory even in the case that the processing time of the data is not fixes. SOLUTION: A device for processing the data and writing the result to the memory is provided with a differentiation circuit 21 for detecting the change of the data and judging the timing of starting the processing of the data to be written in the memory 3, a counter 22 for being reset by the output of the differentiation circuit 21 and counting the time required for the processing of the data to be written in the memory 3, a detection circuit 23 for detecting that the value of the counter 22 is a prescribed value or higher and a memory read control part 24 for reading the data from the memory 3 when it is detected that the value of the counter 22 is the prescribed value or higher by the detection circuit 23 and the read of the data is requested.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory interface for performing a data read operation from a memory using an idle time of a data write process to the memory.

[0002]

2. Description of the Related Art Conventionally, writing and reading of data to and from a memory are managed by a control device such as a CPU. Usually, while performing a main operation of processing data and writing a result to the memory, sometimes an interrupt process is performed. The main operation is suspended to read data. That is, even when the priority is given to writing data to the memory, a wait signal is generated when data is being read from the memory, the writing is temporarily stopped, and the reading time is secured. .

Japanese Patent Application Laid-Open No. Hei 4-133141 proposes a technique for measuring the access time of a memory and performing a read control of the memory based on the measured access time. This technique cannot cope with the case where the processing time differs depending on the data to be written.

[0004]

If the data to be written to the memory is, for example, an address at the start position of the data and run-length data indicating the length of the data, the data is processed and the result is written to the memory. The device has a long idle time between writes for data with a long run length, while an idle time hardly occurs between writes for data with a short run length. As described above, in a device that processes data and writes the result in a memory, when the processing time of the data is not constant, a so-called cycle steal that performs a data read operation using the data write operation is used. This is not always possible.

The present invention has been made in view of such a point, and even when the data processing time is not constant, the main operation of processing the data and writing the result to the memory is stopped. It is an object of the present invention to provide a memory interface that enables data to be read from a memory without causing the data to be read.

[0006]

According to the memory interface of the present invention, in order to solve the above problems, FIG.
As shown in FIG. 2, in a device for processing data and writing the result to a memory, a change in data is detected and the
A differentiating circuit 21 for determining the timing of starting the processing of the data to be written into the memory 3, a counter 22 for counting the time required for processing the data that is reset by the output of the differentiating circuit 21 and written to the memory 3, and the counter 22
Detection circuit 23 for detecting that the value of
And a memory read control unit 24 for detecting that the value of the counter 22 is equal to or greater than a predetermined value by the detection circuit 23 and reading data from the memory 3 when a data read request is issued. is there. here,
The data written to the memory 3 is, for example, an address of a data start position and run-length data indicating the length of the data. When the time required for data processing varies depending on the run-length, the present invention is used. It is particularly preferred if applied.

[0007]

FIG. 1 shows a circuit configuration example of a memory interface according to the present invention. In the figure, 1 is a control unit,
2 is a memory interface and 3 is a memory. When the memory read signal Read changes from the High level to the Low level while the chip select signal CS is at the Low level, the memory 3 performs an operation of reading the data of the memory address specified by the address bus to the data bus. When the chip select signal CS is at a low level, the memory write signal Write is set to a high level.
When the level changes from the low level to the low level, an operation of writing data on the data bus to a memory address specified by the address bus is performed. The memory interface 2 is interposed between the control unit 1 and the memory 3, and when there is a read request from the control unit 1, even if the memory 3 is performing a write operation,
By automatically detecting the timing at which no data is written and reading the data from the memory 3 within the detected readable time width, the main operation of processing the data and writing the result to the memory 3 is stopped. This makes it possible to read data from the memory 3 without any need.

FIG. 2 is an operation waveform diagram of the memory interface shown in FIG. In this example, run-length data of data is extracted and stored in the memory 3. By two consecutive writings, an address indicating the start position of the data and information on the length of the data are stored. are doing. The reading side is also a system that executes reading twice. The reason that the writing side shifts the data by two steps is that
This is for a system that writes data twice consecutively.

First, the operation (a) at the time of writing will be described. In the figure, B, I, O, S, etc. are data of an address indicating the start position of the data, followed by a, d,
f,... mean the data length (run-length data). For example, B, a as memory write data
Means that the address of the data start position is B, and the length of data starting from the address B is a. These data B and a are stored at addresses 0 and 1 of the memory 3, respectively.
Is written continuously. Further, I and d as the memory write data are such that the address of the data start position is I
Means that the length of data starting from the address I is d. These data I and d are stored in the memory 3
Are written successively at addresses 2 and 3 of FIG. Similarly, O and f as the memory write data means that the address of the start position of the data is O and the length of data starting from the address O is f. These data O and f are continuously written to addresses 4 and 5 of the memory 3.

At the timing when the memory write signal falls, the chip select signal CS of the memory 3 is at the low level, and the address data B is written to the address 0 of the memory 3 at the first fall of the memory write signal. At the falling edge of the second memory write signal, the data a is written to the address 1 of the memory 3. After a while, at the falling edge of the third memory write signal, the address data I is changed to the address 2 of the memory 3. At the fourth falling edge of the memory write signal, the data d is written to the address 3 of the memory 3, and after a while, at the fifth falling edge of the memory write signal,
Address data O is written to address 4 of memory 3, and data f is written to address 5 of memory 3 at the falling edge of the sixth memory write signal.

Next, the read operation (b) will be described. At the timing when the memory read signal falls, the chip select signal CS of the memory 3 is at the low level. If the memory address is 0 while the memory read signal is at the low level, the memory 3
Is read as memory read data B, and when the memory address becomes 1, the data at address 1 of the memory 3 is read as memory read data Ba. Here, the data Ba means that the length of the data starting from the address B is a.
Next, during the period when the memory read signal is at the low level, if the memory address is 2, the data at the address 2 of the memory 3 is read as the memory read data I, and if the memory address becomes 3, the address of the memory 3 is read. 3 is read as memory read data Id. Here, the data Id means that the length of data starting from the address I is d.

As apparent from the above description, in the operation waveform of FIG. 2, the memory addresses 0, 1, 2, 3, 4,
.. Indicate the addresses of the memory 3, and FIG.
, Addresses A, B, C,...
U, V, W,... Indicate the addresses of the second memory in which the start position of data and the length of data are stored in the memory 3. By reading the address B of the data start position from the memory addresses 0 and 1 of the memory 3 and the length a of the data, it is understood that the data having the length a from the address B of the second memory is stored. It has a mechanism. Similarly, by reading the start address I of data and the length d of the data from the memory addresses 2 and 3 of the memory 3, the length d from the address I of the second memory is read.
Is stored.

Here, the function of the memory interface is to realize the operation (a) at the time of writing and the operation (b) at the time of reading shown in FIG. (I)
As shown in the figure, the memory addresses are 0, 1, 2, 3, 4,
.., And the memory write data is sequentially changed as B, a, I, d, O, f,. Conventionally, when a read request to the memory 3 is generated from the control unit 1 during the execution of such a memory write operation, a series of memory write operations is temporarily stopped, and a read operation shown in FIG. By performing the operation, data was read from the memory 3. However, as can be seen from the operation at the time of memory writing in FIG. 2A, after writing data B and a at addresses 0 and 1 of the memory 3 by two consecutive memory write signals, a while, Then, data I and I are stored in the addresses 2 and 3 of the memory 3 again by two consecutive memory write signals.
While writing d, during this time, the address of the memory 3 is held in the state of the address 2 in preparation for the next writing, and the data a written last is held as the write data to the memory 3.

The reason why such a state occurs is that, in the case of this embodiment, it is based on the specific situation that the data stored in the memory 3 is run-length data. This is because it takes time before the start address I of the next data and before the start address O of the next data. Of course, even in another system different from this embodiment, there may be a vacant time during which the address and data of the memory do not change during the write operation.

Therefore, in the present invention, the operation at the time of writing (A) and the operation at the time of reading (B) in the operation waveform of FIG.
As shown in (c) of FIG. 2, even during a write operation, a time during which the address and data of the memory 3 are vacant is detected, and a read operation is performed at that time. . In this example, for the sake of simplicity, the operation of reading data written by the immediately preceding write operation is performed. However, an operation of reading another data may be performed.

Hereinafter, the operation of FIG. 2C will be described. At the timing when the memory write signal falls, the chip select signal CS of the memory 3 is at the Low level, and at the fall of the first memory write signal, the data B is written to the address 0 of the memory 3 and the second time. At the falling edge of the memory write signal, data a is stored in memory 3
Is written to the address 1. When the memory address becomes 0 while the chip select signal CS of the memory 3 remains at the Low level, and the memory read signal goes to the Low level,
When the data at the address 0 of the memory 3 is read as the memory read data B and the memory address becomes 1, the data at the address 1 of the memory 3 becomes the memory read data a.
Is read as Chip select signal C of memory 3
S and the memory read signal become High level, and after a while, the chip select signal CS of the memory 3 is returned again.
Becomes Low level, at the third falling edge of the memory write signal, the data I is written to the address 2 of the memory 3, and at the fourth falling edge of the memory write signal, the data d is written to the address 3 of the memory 3. . Memory 3
When the memory address becomes 2 while the chip select signal CS remains at the low level and the memory read signal goes low, the data at the address 2 of the memory 3 is read out as the memory read data I, and when the memory address becomes 3 , The data at the address 3 of the memory 3 is read as the memory read data d. The chip select signal CS and the memory read signal of the memory 3 go to the high level, and after a while, the chip select signal CS of the memory 3 goes to the low level again, and the data O becomes the memory at the falling edge of the fifth memory write signal. The data f is written to the address 4 of the memory 3 at the falling edge of the sixth memory write signal.

Incidentally, it is not always possible to combine such a write operation and a read operation. The reason for this is based on the specific situation that the data stored in the memory 3 is run-length data in this embodiment, and the start position and the length of the data are stored in the memory 3. If the data interval is long enough, there will be a vacant time before the start position of the next data and the timing to store the length, but if the data interval is short, the start position of the next data will be Since the timing for storing the length comes soon, there is no sufficient free time. For example, referring to the operation waveform of FIG. 2, the start position of data is address B and the length of the data is a, and the start position of data is address I and the length of the data is d In the case of, there is sufficient free time, but if the start position of the data is address O and the length of the data is f, the start position (address S) of the next data There is not enough time between them, and no read operation can be inserted during that time.

In this embodiment, instead of simply performing the write operation and the read operation alternately, as shown in FIG. 1, a differentiating circuit 21, a counter 22, a detecting unit 23,
A memory read control unit 24 is provided to automatically determine whether a memory read operation is possible. The method of detecting the time width on the read side is as follows. A differentiating circuit 21 is constituted by the input data shown in the read operation (b) of FIG. 2 and the data shift 1 obtained by delaying this by one cycle by the shift register. An enable signal is output for one clock cycle on the falling side. That is, the differentiating circuit 21 outputs a High level signal only during a period in which the data shift 1 is at High level and the input data is at Low level. This signal is used as a counter 2 for timing counting.
2, the counter 22 is reset at the falling edge of the signal. When the value of the counter 22 of the timing count becomes 4 or more (a time width of 5 cycles is required for performing two readings), a reading operation is performed. Even when a series of reading is completed, if the value of the timing counting counter 22 is 4 or more, reading is continuously performed. Therefore, when the free time is short due to the writing of the data with the short interval between the start addresses, and the data cannot be read at that time, but when the free time is long due to the writing of the data with the long interval between the start addresses, Data can be read many times. This repetition is controlled by the memory address on the reading side and the memory address on the writing side, so that the address on the reading side does not exceed the address on the writing side.

Next, specific applications of the above-described hardware will be described with reference to an example. .. In FIG. 3 (a) indicate pixel addresses of the image memory, which correspond to the addresses A, B, C, D,. Assume that data obtained by binarizing each pixel in the image memory of FIG. 3A is as shown in FIG. 3B, for example. A white square □ in FIG. 3B indicates that the data obtained by binarizing the pixel value of the pixel address is 0, and a black square 図 in FIG. 3B indicates that the pixel value of the pixel address is binary. This means that the converted data is 1. It is assumed that this corresponds to the data 1 and 0 which are described below the addresses A, B, C, D,... In FIG. Next, in the list data B, 2, I, 2, O, 1, S, 1,... Shown in FIG. 3C, there are two data from the pixel address B in FIG. However, this means that two data exist from the pixel address I, one data exists from the pixel address O, and one data exists from the pixel address S. Corresponding to the data stored in. If there are many white backgrounds or large run length data in the binarized data, there is a merit to create the data of the list structure in FIG.

Now, for such an application, a method of detecting the start position of data and the length of data will be described with reference to FIG.
Will be described with reference to the operation (a) at the time of writing. In FIG. 2A, data shift 2 is data obtained by delaying input data by two cycles by a shift register, and data shift 3 is data obtained by delaying input data by three cycles by a shift register. When the data shift 3 rises, the position data fetch timing signal rises, and the position data fetch timing signal falls in one cycle. At this time, the length count is started at the same time as the position data of the start address is fetched. Next, when the data shift 3 falls, the length detection timing signal rises, and the data of the length count is read. The length detection timing signal falls in one cycle, and at this time, the length count data is reset.

[0021]

According to the first aspect of the present invention, in a device for processing data and writing the result to a memory, a differential for detecting a change in data and judging a timing to start processing of data to be written to the memory. A counter that counts the time required for processing the data that is reset by the output of the differentiating circuit and written to the memory; a detection circuit that detects that the value of the counter is equal to or greater than a predetermined value; A memory read control unit that reads data from the memory when the value is detected to be equal to or greater than a predetermined value and there is a data read request. Without stopping the operation, when there is a read request, the circuit itself can automatically detect the time width and read the data. Kill.

According to the second aspect of the present invention, the data to be written into the memory is the address of the start position of the data and the run-length data indicating the length of the data. Therefore, if the memory interface of the present invention is used, the main operation of processing the data and writing the result to the memory is not affected at all, and is caused by the processing of the data having a long run length. A memory read operation can be performed using the idle time.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of a memory interface of the present invention.

FIG. 2 is an operation waveform diagram of the memory interface of the present invention.

FIG. 3 is an operation explanatory diagram when the memory interface of the present invention is applied to image processing.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Control part 2 Memory interface 3 Memory 21 Differentiating circuit 22 Counter 23 Detection circuit 24 Memory read control part

Claims (2)

[Claims] An apparatus for processing data and writing the result to a memory, comprising: a differential circuit for detecting a change in the data to determine a timing for starting processing of the data written to the memory; A counter that counts the time required to process the data written to the memory, a detection circuit that detects that the value of the counter is greater than or equal to a predetermined value, and that the value of the counter is greater than or equal to the predetermined value by the detection circuit. A memory interface comprising: a memory read control unit that detects data and reads data from a memory when a data read request is issued. 2. The data written to the memory is an address of a data start position and run-length data indicating the length of the data, and the time required for data processing varies according to the run-length. Claim 1
Memory interface.