JP3700504B2 - Memory interface - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a memory interface for performing a data read operation from a memory by using a free time of a data write process to the memory.
[0002]
[Prior art]
Conventionally, the writing and reading of data to and from the memory are managed by a control device such as a CPU. Usually, the main operation is temporarily performed by interrupt processing while processing the data and writing the result into the memory. Stopping and reading data is performed. That is, even if priority is given to writing data to the memory, a waiting signal is generated when data is being read from the memory, and writing is temporarily stopped to ensure the reading time. .
[0003]
Japanese Patent Application Laid-Open No. 4-133141 proposes a technique for measuring the memory access time and performing memory read control based on the measured memory access time, which deals with the case where the access time differs depending on the type of memory. This is a technology and cannot be handled when the processing time differs depending on the data to be written.
[0004]
[Problems to be solved by the invention]
If the data written to the memory is, for example, run-length data indicating the address of the start position of the data and the length of the data, the device that processes the data and writes the result to the memory is not long-run data. While a long idle time occurs during writing, data having a short run length hardly causes an idle time during writing. In this way, in a device that processes data and writes the result to the memory, if the data processing time is not constant, a so-called cycle steal that performs a data read operation using the data write operation is performed. It is not always possible.
[0005]
The present invention has been made in view of such points, and even when the data processing time is not constant, the main operation of processing the data and writing the result into the memory is not stopped. An object of the present invention is to provide a memory interface capable of reading data from a memory.
[0006]
[Means for Solving the Problems]
According to the memory interface of the present invention, in order to solve the above problem, as shown in FIG. 1, in a device that processes data and writes the result in the memory, a change in the data is detected and written in the memory 3. Differentiating circuit 21 for determining the timing of starting the processing of the data to be processed, a counter 22 for counting the time required for processing the data that is reset by the output of the differentiating circuit 21 and written to the memory 3, and the value of the counter 22 is predetermined. A detection circuit 23 that detects that the value is equal to or greater than the value, and a memory read control unit that reads the data from the memory 3 if the detection circuit 23 detects that the value of the counter 22 is equal to or greater than the predetermined value and there is a data read request. 24. Here, the data written in the memory 3 is, for example, the address of the start position of the data and the run length data indicating the length of the data, and the time required for processing the data varies depending on the run length. It is particularly preferable to apply the present invention.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows a circuit configuration example of a memory interface of the present invention. In the figure, 1 is a control unit, 2 is a memory interface, and 3 is a memory. If the memory read signal Read changes from the High level to the Low level when the chip select signal CS is at the Low level, the memory 3 performs an operation of reading data at the memory address specified by the address bus to the data bus. Further, when the memory select signal Write changes from the High level to the Low level when the chip select signal CS is at the Low level, the operation of writing data on the data bus to the memory address specified by the address bus is performed. The memory interface 2 is interposed between the control unit 1 and the memory 3, and when there is a read request from the control unit 1, the timing at which data is not written is automatically detected even if the memory 3 is performing a write operation. Then, by reading the data from the memory 3 with the detected readable time width, the data can be read from the memory 3 without stopping the main operation of processing the data and writing the result into the memory 3. Make it possible.
[0008]
FIG. 2 is an operation waveform diagram of the memory interface shown in FIG. In this example, the run length data of the data is extracted and stored in the memory 3, and the address indicating the start position of the data and the length information following the data are stored by two consecutive writes. doing. The reading side is also a system that executes two readings. The writing side shifts the data by two stages because it is a system that writes data continuously twice.
[0009]
First, the operation (a) at the time of writing will be described. In the figure, B, I, O, S, etc. are data at addresses indicating the start position of data, and a, d, f,... Following the data mean the length of data (run-length data). For example, B and a as memory write data means that the address of the data start position is B and the length of data starting from this address B is a. These data B and a are written continuously at addresses 0 and 1 of the memory 3. Further, I and d as memory write data means that the address of the start position of data is I and the length of data starting from this address I is d. These data I and d are written continuously at addresses 2 and 3 of the memory 3. Similarly, O and f as memory write data means that the address of the start position of data is O and the length of data starting from this address O is f. These data O and f are written continuously at addresses 4 and 5 of the memory 3.
[0010]
At the timing when the memory write signal falls, the chip select signal CS of the memory 3 is at the low level, and at the fall of the first memory write signal, the address data B is written to the address 0 of the memory 3 and the second time. The data a is written to the address 1 of the memory 3 at the falling edge of the memory write signal, and the address data I is written to the address 2 of the memory 3 at the falling edge of the third memory write signal after a while. The data d is written to the address 3 of the memory 3 at the falling edge of the fourth memory write signal. After a while, the address data O becomes the address 4 of the memory 3 at the falling edge of the fifth memory write signal. And data f is written to address 5 of the memory 3 at the falling edge of the sixth memory write signal. It is.
[0011]
Next, the operation (b) at the time of reading will be described. At the timing when the memory read signal falls, the chip select signal CS of the memory 3 is at the low level. When the memory read signal is low level, if the memory address is 0, the data at address 0 in the memory 3 is read as the memory read data B, and if the memory address is 1, the data at address 1 in the memory 3 is read. Is read as memory read data Ba. Here, data Ba means that the length of data starting from address B is a. Next, in the period when the memory read signal is at the low level, if the memory address is 2, the data at address 2 of the memory 3 is read as the memory read data I, and if the memory address becomes 3, the address of the memory 3 is read. 3 data is read as memory read data Id. Here, data Id means that the length of data starting from address I is d.
[0012]
As apparent from the above description, in the operation waveform of FIG. 2, the memory addresses 0, 1, 2, 3, 4, 5, 6,... Indicate the addresses of the memory 3, and 2 from the top of FIG. The addresses A, B, C,..., U, V, W,... Described in the row indicate the addresses of the second memory in which the data start position and the data length are stored in the memory 3. ing. By reading the address B of the data start position from the memory addresses 0 and 1 of the memory 3 and the length a of the data, it can be seen that the data of the length a is stored from the address B of the second memory. It is a mechanism. Similarly, by reading the data start address I and the data length d from the memory addresses 2 and 3 of the memory 3, data of the length d from the address I of the second memory is stored. It is a mechanism to understand.
[0013]
Here, the function of the memory interface is to realize the operation (a) at the time of writing and the operation (b) at the time of reading (b) shown in FIG. As shown, the memory address is sequentially changed as 0, 1, 2, 3, 4, 5,..., And the memory write data is sequentially changed as B, a, I, d, O, f,. I am letting. When a read request to the memory 3 is generated from the control unit 1 while such a memory write operation is being performed, conventionally, a series of memory write operations are temporarily stopped to perform a read operation shown in FIG. Data was read from the memory 3 by performing the operation. However, as can be seen from the operation at the time of memory writing in FIG. 2A, after data B and a are written to the addresses 0 and 1 of the memory 3 by two consecutive memory write signals, there is a short pause. Then, the data I and d are written to the addresses 2 and 3 of the memory 3 again by two consecutive memory write signals. During this time, the address of the memory 3 is held in the address 2 state in preparation for the next writing. As the data written to the memory 3, the last written data a is held.
[0014]
The reason why such a state occurs is, in the case of this embodiment, based on the specific situation that the data stored in the memory 3 is run-length data. This is because it takes time until the next start address I and further until the start address O of the next data. Of course, even in another system different from this embodiment, it is possible that an idle time in which the memory address and data do not change occurs during the write operation.
[0015]
Therefore, in the present invention, as shown in (c) of FIG. 2, by combining the operation at the time of writing (A) and the operation at the time of reading (B) in the operation waveform of FIG. The time when the address and data in the memory 3 are free is detected, and the read operation is performed at that time. In this example, in order to simplify the explanation, the operation of reading the data written by the immediately preceding write operation is performed, but the operation of reading another data may be performed.
[0016]
Hereinafter, the operation of FIG. 2C will be described. At the timing when the memory write signal falls, the chip select signal CS of the memory 3 is at the low level, and at the fall of the first memory write signal, the data B is written to the address 0 of the memory 3 and the second time. Data a is written to address 1 of the memory 3 at the falling edge of the memory write signal. When the chip select signal CS of the memory 3 remains low level, the memory address becomes 0, and when the memory read signal becomes low level, the data at address 0 of the memory 3 is read as the memory read data B, and the memory address is 1 Then, data at address 1 in the memory 3 is read as memory read data a. The chip select signal CS and the memory read signal of the memory 3 become the high level, and after a while, the chip select signal CS of the memory 3 again becomes the low level, and the data I is stored in the memory at the fall of the third memory write signal. 3 is written to address 2 and data d is written to address 3 of the memory 3 at the falling edge of the fourth memory write signal. When the chip select signal CS of the memory 3 remains low level, the memory address becomes 2, and when the memory read signal becomes low level, the data at the address 2 of the memory 3 is read as the memory read data I, and the memory address is 3 Then, data at address 3 in the memory 3 is read as memory read data d. The chip select signal CS and the memory read signal of the memory 3 become the high level, and after a while, the chip select signal CS of the memory 3 becomes the low level again, and the data O becomes the memory at the falling edge of the fifth memory write signal. 3 is written to address 4 and data f is written to address 5 of the memory 3 at the falling edge of the sixth memory write signal.
[0017]
By the way, it is not always possible to combine such a write operation and a read operation. The reason for this is based on the specific situation that the data stored in the memory 3 is run-length data in this embodiment, and the start position and length of the data are stored in the memory 3. Sometimes, if the data interval is long enough, there will be free time before the next data start position and the timing to store the length, but if the data interval is short, the next data start position Since the timing for storing the length comes immediately, there is not enough free time. For example, referring to the operation waveform of FIG. 2, the data start position is address B and the data length is a, and the data start position is address I and the data length is d. In the case where there is sufficient free time, when the data start position is the address O and the length of the data is f, the next data start position (address S) is reached. There is not enough time between them and no read operation can be inserted between them.
[0018]
Therefore, in this embodiment, instead of simply performing the write operation and the read operation alternately, as shown in FIG. 1, a differentiation circuit 21, a counter 22, a detection unit 23, and a memory read control unit 24 are provided, Whether the read operation is possible is automatically determined. The method of detecting the time width on the read side is configured by configuring the differentiation circuit 21 by the input data shown in the operation (b) at the time of reading in FIG. 2 and the data shift 1 delayed by one cycle by the shift register. On the lower side, an enable signal is output for one clock cycle. That is, the differentiation circuit 21 outputs a high level signal only during a period when the data shift 1 is at a high level and the input data is at a low level. This signal is used as a reset signal for the counter 22 for timing counting, and the counter 22 is reset at the falling timing of the signal. When the value of the counter 22 of the timing count becomes 4 or more (a time width of 5 cycles is necessary for performing the reading twice), the reading operation is performed. Even when a series of reading is finished, if the value of the counter 22 for timing count is 4 or more, the reading is continued. Therefore, there is little free time by writing data with a short start address interval, and even when data cannot be read at that time, when there is a lot of free time after writing data with a long start address interval, Data can be read many times. This repetition is controlled by the memory address on the reading side and the memory address on the writing side, so that the address on the reading side does not exceed the address on the writing side.
[0019]
Next, an example of how the above hardware can be applied will be described. In FIG. 3A, A, B, C, D,... Mean pixel addresses of the image memory, and these correspond to the addresses A, B, C, D,. Assume that the data obtained by binarizing each pixel of the image memory in FIG. 3A is as shown in FIG. The white square □ in FIG. 3B means that the data obtained by binarizing the pixel value of the pixel address is 0, and the black square ■ in FIG. 3B is a binary value of the pixel address of the pixel address. It means that the digitized data is 1. It is assumed that this corresponds to data 1 and 0 shown below addresses A, B, C, D,. Next, the list data B, 2, I, 2, O, 1, S, 1,... Shown in FIG. 3 (c) has two data from the pixel address B in FIG. This means that there are two data from the pixel address I, one data from the pixel address O, and one data from the pixel address S, which is the memory 3 in FIG. Corresponds to the data stored in. When the binarized data has many white backgrounds or data with a large run length, there is an advantage of creating data having a list structure shown in FIG.
[0020]
Now, for such applications, a method for detecting the start position of data and the length of data will be described with reference to the write operation (a) in FIG. In FIG. 2A, data shift 2 is data obtained by delaying input data by two cycles by the shift register, and data shift 3 is data obtained by delaying input data by three cycles by the shift register. When the data shift 3 rises, the position data take-in timing signal rises and the position data take-in timing signal falls in one cycle time. At this time, the position data of the start address is fetched, and at the same time, the length count is started. Next, when the data shift 3 falls, the length detection timing signal rises and the length count data is read. The length detection timing signal falls in one cycle time, and at this time, the length count data is reset.
[0021]
【The invention's effect】
According to the first aspect of the present invention, in the device for processing data and writing the result into the memory, the differentiation circuit for detecting the change of the data and determining the timing of starting the processing of the data written to the memory, and the differentiation circuit Counter that counts the time required to process the data that is reset and output to the memory, a detection circuit that detects that the value of the counter is greater than or equal to a predetermined value, and a counter value that is greater than or equal to the predetermined value by the detection circuit And a memory read control unit that reads data from the memory if there is a data read request, the main operation of processing the data and writing the result into the memory is stopped. If there is a read request, the circuit can automatically detect the time width and read the data.
[0022]
According to the second aspect of the present invention, the data to be written in the memory is the data of the start position of the data and the run length data indicating the length of the data, and the time required for processing the data varies depending on the run length. Therefore, if the memory interface of the present invention is used, the free time caused by the processing of data with a long run length can be reduced without affecting the main operation of processing the data and writing the result into the memory. A memory read operation can be performed by using this.
[Brief description of the drawings]
FIG. 1 is a circuit configuration diagram of a memory interface of the present invention.
FIG. 2 is an operation waveform diagram of the memory interface of the present invention.
FIG. 3 is an operation explanatory diagram when the memory interface of the present invention is applied to image processing;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Control part 2 Memory interface 3 Memory 21 Differentiation circuit 22 Counter 23 Detection circuit 24 Memory read control part

Claims (2)

In a device that processes data and writes the result to memory, a differentiation circuit that detects a change in data and determines the timing of starting processing of data written to the memory, and is reset by the output of the differentiation circuit and written to the memory A counter that counts the time required to process the data to be processed, a detection circuit that detects that the value of the counter is greater than or equal to a predetermined value, and the detection circuit detects that the value of the counter is greater than or equal to the predetermined value and data And a memory read control unit that reads data from the memory when there is a read request. The data written in the memory is run-length data indicating the address of the start position of the data and the length of the data, and the time required for processing the data varies according to the run-length. Memory interface.

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