JPH01228375A - Image processing rum length coding circuit - Google Patents

Abstract

PURPOSE:To shorten time required for measurement/misrecognition of a binary image by constituting the title circuit so that the access of a processor can be executed even on the way of a processing by using an FIFO memory. CONSTITUTION:In an X.FIFO memory 24, an X<->.FIFO memory 25 and a Y.FIFO memory 26, (x) coordinate data of the leading end of the rise of a binary image signal PD, X coordinate data of the trailing end of the fall of the binary image signal PD and Y coordinate of the leading end of the rise of the binary image signal PD are stored, respectively. In such a way, the foregoing is repeated until one screen is ended. As for these coordinate data stored in respective memories 24-26, as soon as the data are written in each FIFO memory in accordance with a processing procedure stored in a memory 28 through a control bus 20 under the control of a processor 27, they are read out through a data bus 19, and stored in the memory 28. In such a way, to the data stored in respective memories 24-26, a prescribed operation processing is performed by the processor 27 and an image is reproduced, and a necessary processing is executed and said data are outputted to an output terminal 22 through an I/O terminal 29.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to image processing run length encoding circuits.

(Prior Art) In order to facilitate understanding of the explanation of the conventional image processing run-length encoding circuit, we will first explain the run-length code, which is an m-information compression method for binary images, using FIGS. The conversion process will be explained.

FIG. 5 shows a binary image assuming one screen.

The horizontal axis is the X coordinate, and the vertical axis is the Y coordinate. The number of pixels on the X coordinate is 8 pixels from 0 to 7, and the number of pixels on the Y coordinate is 7 pixels from 0 to 6. An example will be described in which the image is located in the shaded pixel area.

The length of the image starting from (X=1, Y=O) is L=1, then the length of the image starting from (X=3, Y-0) - is L=2, etc. etc., and the coded version of the image shown in FIG. 5 is shown in FIG. 6(a).

Furthermore, instead of the length L, encoding processing may be performed as a method of determining the end point χ- of the image.

The processing result in this case is shown in FIG. 6 (b), which means that L=
χ−1χ, which is a mathematically equivalent expression.

Note that NOl shown in FIG. 6 is numbered from ■ to ■ in FIG.
It corresponds to

Next, a conventional image processing run-length encoding circuit realized by the expression shown in FIG. 6(b) will be explained using FIG. 8.

In this case, to simplify the explanation, as shown in FIG.
A case will be described in which there is an image that continues up to x−χ−).

The X coordinate generator 10 has a horizontal synchronizing signal H3 at this clear end CLH, and a pixel clock PC at clocks r4AcI and K.
LK are respectively input, and the output iQ outputs an X coordinate signal corresponding to the pixel clock PCLK.

In the Y coordinate generator 11, the vertical synchronization signal vS is input to this clear @cLR, the horizontal synchronization signal H3 is input to the clock terminal CLK, and the vertical synchronization signal ■S is input from the output #iQ.
Outputs a Y coordinate signal corresponding to .

12 is a run decoder, the pixel clock PCLK is input to the clock terminal CLK, the binary image shown in FIG. 7 is input to the image input terminal P, and the vertical synchronization signal vS is input to the output @Q+. is the address signal ER indicating the number of runs, the output terminal Q2 is the total number of runs RT (this is set to zero by the vertical synchronization signal S), and the control terminal C is the memory control signal MC that controls the memory. are output respectively.

The X memory 13 is a driver 13A for writing the X coordinate (X=χ) of the starting end of the image from the output end Q of the X coordinate generator 10.
The data is inputted to the data end of the X memory 13 via. In the Y memory 14, the Y coordinate (Y=y') from the output end Q of the Y coordinate generator 1 is inputted to data 9D of the Y memory 14 via the write driver 13B. Furthermore, 15 is X-
The X coordinate signal <X=χ-) at the end χ of the image from the output end Q of the X coordinate generator 10 is input to the data end of the X memory 15 via the writing driver 13C. Ru.

These X memory 13, Y memory 14, and X-memory 15 are connected from the control end C of the run decoder 12 to the driver 1.
Memory control signal MC1 output ff output via 3D
Addresses, data, and writing/reading of each memory are controlled by address signal ER outputted from fAQ via drivers 13G, 132, and 13K.

The processor 16, memory 17, and I10 terminal 18 are each connected to a data bus 19, a control bus 20, and an address bus 21, and further connected to the processor 1
A vertical synchronizing signal vS is input to 6. (10) From the terminal 18, the processing result of image processing performed by the processor 16 is outputted to the output terminal 22.

Further, the address bus 21 is connected to the drivers 13H113J, 1
The control bus 20 connects the X memory 13, Y memory 14, and X memory 15 to the address end A of the processor 16 via the driver 13B. - control memory 15; Further, each data bus 19 has an X memory 13
, Y memory 14, X-memory 15, and run decoder 12 through drivers 14A, 14B, and 14C 113F under the control of processor 16.

Next, the operation of the image processing run-length encoding circuit shown in FIG. 8 and configured as described above will be explained.

The processing procedure can be roughly divided into two: a run-length encoding processing procedure and a processor (CPU) access procedure.

First, the run-length encoding processing procedure will be explained.

First, the run decoder 12 outputs a memory control signal M and an address signal ER to control the X memory 13, Y memory 14, and x'' memory 15, and input of one screen is started.

First, during the synchronization period of the vertical synchronization signal VS, the run decoder 1
Set the number of runs in 2 to zero.

Next, by inputting the image, the run decoater 12
The starting edge (X=Z, Y-'/) of the binary image is detected and written to the X memory 13 and Y memory 14, respectively.

Third, the end of this binary image (X=χ-1Y=y) is detected by the run decoder 12 and the X% eFf at this point is
=χ- is written into the X memory 15.

Next, the run decoder 12 increments the number of runs it has counted by +1.

Input for one screen is completed in the above manner. At this point, the total number of run decoders 12 is 1 as shown in FIG.
It becomes.

This completes the run-length encoding processing procedure.

Next, the process moves to the access hand 111N to the processor (CPU).

When the input for one screen is completed, the processor 16 detects a change in the level of the vertical synchronizing signal vS, and thereby the processor 16 gains access rights to the X memory 13, Y memory 14, and X-memory 15.

Next, the processor 16 outputs the output terminal Q2 of the run decoder 12.
The total number of runs RT (in this case, the total number is 1) is read into the memory 17 via the driver 13F.

Furthermore, the processor 16 stores X memory 1 for the total number of runs.
3. Read data from the Y memory 14 and the X-memory 15 into the memory 17.

Thereafter, using these data read into the memory 17, image measurement/recognition is executed by software processing according to the calculation procedure stored in advance in the memory 17, and the results are sent to the I10 terminal 18. The signal is outputted to the output end 22 via the signal line.

After this, the access right is transferred again to the run-length encoding processing procedure side, and reading of the image is started.

In this way, image processing is executed by repeating the access procedure to the processor (CPU) and the run-length encoding processing step II.

<Problems to be Solved by the Invention> However, as can be seen from the above operation, such an image processing run-length encoding circuit is configured to transfer access rights to each memory to the processor 16 after one screen is completed. , the processor 16 reads the run data, so the minimum time for analyzing a run (software processing) is never less than one screen (one frame, or one field);
It is not possible to improve processing speed faster than screen processing.

Means for Solving the Problems> In order to solve the above problems, the present invention firstly provides an X-coordinate generator that generates an X-coordinate signal from an image horizontal synchronization signal and a pixel clock, A Y-coordinate generator that generates a Y-coordinate signal from the signal and the vertical synchronization signal of the image, and a start edge detection signal that receives the binary image signal of the image and the pixel clock and detects the starting edge coordinate of the rising edge of this binary image signal. and a run decoder that outputs a terminal detection signal for detecting the terminal coordinate of the falling edge of a binary image, and an FIFO memory, YFi mark signal and start edge detection signal are input and Y when this start edge detection signal is generated.
A Y-FIFO memory that stores coordinates, an X-FIFO memory that stores an X-coordinate when an X-coordinate signal and an end detection signal are input and the end detection signal is generated, and reading from these FIFO memories. The apparatus is equipped with a processor which reads coordinate data stored in these FIFO memories arbitrarily and performs image recognition by detecting a possible signal.

Second, in addition to the first configuration, this
The memory has a data input terminal to which the XM mark signal and the start edge detection signal are input, and the output of a second length circuit for calculating the length of the image is applied thereto.

Thirdly, in addition to the first configuration, the X-FIFO memory has an image clock and a start edge detection signal input to its data input terminal, and the output of a second length circuit that calculates the length of the image is applied. This is how it was done.

Function> An X-FIFO memory in which XFi marks are stored one after another each time a start edge detection signal of images inputted one after another is generated;
A Y-FIFO memory that stores the Y-coordinate each time this image start-edge detection signal occurs, and an X-FIFO memory that stores the X-coordinate each time the image end-detection signal occurs.
The contents of each FO memory are stored in these FIs by the processor.
By detecting a read enable signal from the FO memory, each corresponding coordinate data stored in these FIFO memories is arbitrarily read out from each FIFO memory and used to sequentially perform image recognition.

<Example> Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. Note that parts having the same functions as those of the conventional image processing run-length encoding circuit shown in FIGS. 5 to 8 are given the same reference numerals, and the explanation thereof will be omitted as appropriate.

The X-coordinate generator 10 and the Y-coordinate generator 11 have the same configuration as shown in FIG. 8, and generate X-coordinate and Y-coordinate signals, respectively.

23 is a run decoder to which the pixel clock PCLK and the binary image PD are input, and its output is a starting edge detection signal PS that detects the starting edge coordinates of the rising edge of the binary image signal PD and a binary image f-image signal PD. It outputs a termination detection signal PR for detecting the termination coordinate of the falling edge. Run de coater 23
is composed of a plurality of D-type flip-flops and an AND gate, and the starting edge detection signal PS is transmitted from the D-type flip-flop D-
The termination detection signal PE is detected by a circuit consisting of FF1 and ant game) AND, and the termination detection signal PE is detected by a D type flip-flop D-
It is detected by a circuit composed of FF2 and an AND gate AND2.

The X-FIFO memory 24 receives the X-coordinate signal from the X-coordinate generator 10 at the data end, and also receives from the run decoder 23 a start-edge detection signal PS for detecting the start-edge of an image. Additionally, the stored
The coordinate data is a status signal S indicating whether it can be read.
T + is output and its data is read out from its data output f)l D 2 by a control signal input from the control terminal C.

The X- FIFO memory 25 receives the X from the X coordinate generator 10.
A coordinate signal is input to the data end, and an end detection signal PE is input from the run decoder 23 to detect the end when the image falls. Furthermore, a status signal S indicating whether or not the stored XM standard data can be read is provided.
T2 is output, and the data is read out from the data output terminal D2 by a control signal inputted from the control terminal C.

Further, the Y-FIFO memory 26 receives the Y coordinate signal from the YM reference generator 11 at the data end D1, and also receives from the run decoder 23 a starting edge detection signal PS for detecting the starting edge when the image rises. Furthermore, the stored Y coordinate data when the image starts up outputs an R signal s'r indicating whether or not it can be read out, and the data is output by the control signal input from the control terminal C. Read from D2.

The coordinate data stored in each memory 24, 25, 26 is read out via one data bus via the control bus 2° under the control of the processor 27 in accordance with the processing procedure stored in the memory 28. is stored in When reading from this memory 24, 25, 26, each memory 24
．． Reading of the status signals ST, .about.ST from 25.26 is started based on the processor 27T3.

Using the coordinate data read into each memory, the processor 27 reproduces an image according to a predetermined program stored in the memory 28, performs predetermined processing, and outputs the image to the output terminal 22 via the I10 terminal 29.

Next, the operation of the embodiment shown in FIG. 1 constructed as above will be explained using FIG. 2.

When the input of one screen starts, the X coordinate generator 10 sequentially outputs the
M standard data (FIG. 2(g)) is generated and output to the X-FIFO memory 24 and the X-FIFO memory 25. Then, the horizontal synchronizing signal H3 (Figure 2 (b)) is at the clear end CL.
Every time input is made to R, the contents in the X coordinate generator 10 are cleared and returned to the initial state, and the pixel clock PCLK
X coordinate data is generated sequentially according to (FIG. 2(c)).

On the other hand, the horizontal synchronizing signal H3 (Fig. 2 (b)) is input to the Y coordinate generator 11 as its clock @CLK, and the
Every time a line is scanned, Y-coordinate data is output to the Y-FIFO memory 26, and a vertical synchronization signal vS (Fig. 2 (a))
Each time , the contents are cleared and return to the initial state, and Y coordinate data is again generated sequentially in accordance with the horizontal synchronizing signal H3 (FIG. 2 (b)).

Furthermore, the binary image signal PD (FIG. 2(D)) is input to the run decoder 23 according to the pixel clock PCLK (FIG. 2(C)), and the binary image signal PD is converted as shown in FIG. 2(C). When the X coordinate of the X coordinate data turns on (FIG. 2 (G)), the run decoder 23 sends the starting edge detection signal PS (FIG. 2 (E)) to the X-FIFO memory 24 and the Y-FIFO.
Output to memory 26. Further, when the binary image signal PD falls at the χ゛ coordinate point (FIG. 2(G)) of the X coordinate data as shown in FIG. to)) to X-・FIFO memory 2
Output to 5.

In this way, one binary image is stored in the X-FIFO memory 24.
The X coordinate data of the starting edge of the rising edge of the image signal PD is
The IFO memory 25 stores the X coordinate data of the trailing edge of the binary image signal PD, and the Y-FIFO memory 26 stores the Y coordinate data of the trailing edge of the binary image signal PD.

This process is repeated until one screen is completed.

These coordinate data stored in each memory 24.25.26 are the state signals ST from each memory 24.25.26,
~ST, and then the data bus 19 is written as soon as data is written into each FIFO memory according to the processing procedure stored in the memory 28 via the control bus 20 under the control of the processor 27. and stored in the memory 28.

In this way, the data stored in each memory 24, 25, 26 is subjected to predetermined arithmetic processing by the processor 27 to reproduce an image, and after the necessary processing is performed, it is output to the output terminal 22 via the I10 terminal 29. be done.

In the embodiment shown in Fig. 1, the start coordinates are written in the X-FIFO memory and the end coordinates are written in the X-FIFO memory, but the image run length L is used instead of the end coordinates. You can also do it.

FIG. 3 is a block diagram showing the configuration when storing in the X-FTFO memory using the run length L.

The length circuit 30 includes a latch L A 'T' and a subtractor S
It consists of UB etc. X coordinate data is latch LA
The data end of LAT is input to the data end of T and one input end A of the subtractor SUB, and the data of the latch LAT is taken in at the timing of the start end signal PS, and the data of the output end Q is input to the other input end B of the subtracter SUB. input, and the subtractor S
tJB performs subtraction on the data input to these inputs @A and B, and outputs the length to the output terminal Q.

The end of the image is detected by the X-FIFO memory 25 using the end detection signal PE, and the difference between the end coordinate and the start coordinate at this time is stored as the length L of the image in the X-FIFO memory 25.
is stored in

FIG. 4 is a block diagram showing the configuration of a length circuit 31 that counts from the start coordinate to the end coordinate and outputs the length L of the run.

In this case, the content of the counter CT is cleared by the start edge detection signal PS, the counter CT counts the subsequent pixel clock PCLK, and the count value is detected by the end edge detection signal PE, thereby changing the count value up to that point. The length L of 57 is stored in the X- FIFO memory 25.

<Effects of the Invention> As specifically explained above in conjunction with the embodiments, according to the present invention, by using the FIFO memory, the processor can be accessed even during processing, reducing the time required to measure binary images/several products. can be significantly shortened.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a waveform diagram explaining the operation of the embodiment shown in FIG. 1, and FIG. FIG. 4 is a partial block diagram showing the second configuration of the present invention in the case of storing in the FIFO memory, and FIG. FIG. 5 is an explanatory diagram showing an example of a binary image assuming one screen for explanation; FIG. 6 is an explanatory diagram illustrating a coded image of the image shown in FIG. 5; Fig. 7 is an explanatory diagram of a binary image without assuming a screen to simplify the subsequent explanation, and Fig. 8 is a conventional image processing run-length coding diagram showing a circuit that realizes the image shown in Fig. 7. It is a block diagram of a circuit. 10...X coordinate generator, 11...Y coordinate generator, 1
2...Run decoder, 13...X memory, 14...
・Y memory, 15...X° memory, 16...processor, 17...memory, 18...I10 terminal, 23...run decoder, 24...X-FIFO
Memory, 25...X- FIFO memory, 26...
Y=FIFO memory, 27...processor, 28...
・Memory, 29...■10 terminal, 30.31・
...Length circuit, H8...Horizontal synchronization signal, PCLK
...Image clock, PD...Binary image signal, VS.
...Vertical synchronization signal, PS...Starting edge detection signal, PE...
・Termination detection signal. 3rd figure 4th figure 6th figure...8

Claims (3)

[Claims] (1) an X-coordinate generator that generates an X-coordinate signal from a horizontal synchronization signal of an image and a pixel clock; a Y-coordinate generator that generates a Y-coordinate signal from the horizontal synchronization signal and a vertical synchronization signal of the image; A binary image signal of the image and the pixel clock are input, and a starting edge detection signal detects the starting edge coordinate of the rising edge of the binary image signal, and a trailing edge detection signal detects the ending edge coordinate of the falling edge of the binary image signal. A run decoder that outputs, and an
an IFO memory, a Y/FIFO memory for storing the Y coordinate when the Y coordinate signal and the start edge detection signal are input and the start edge detection signal is generated, and the X coordinate signal and the end edge detection signal are input. An X FIFO memory stores the X coordinate when this end detection signal is generated, and by detecting readable signals from these FIFO memories, the coordinate data stored in these FIFO memories can be arbitrarily stored. an image processing run length encoding circuit comprising a readout image recognition processor; (2) The X^- FIFO memory is configured such that the X coordinate signal and the start edge detection signal are input to its data input terminal, and the output of the first length circuit that calculates the length of the image is applied. An image processing run length encoding circuit according to claim 1, characterized in that: (3) The X^- FIFO memory is configured such that the image clock and the start edge detection signal are input to its data input terminal, and the output of a second length circuit that calculates the length of the image is applied thereto. An image processing run length encoding circuit according to claim 1, characterized in that: