JPH0581052A - Microprocessor runaway check circuit - Google Patents

Abstract

PURPOSE:To supervise the runaway of MPU without connecting a measurement unit such as an emulator to MPU on a microprocessor runaway check circuit checking the runaway of a microprocessor unit (MPU). CONSTITUTION:Respective reference data on start/end, which show the start and end of a command in a program stored in a storage means 11 that is to be executed, are previously set and they are stored in first and second data storage parts 1 and 2. First and second comparison circuits 3 and 4 respectively compare respective stored reference data or start/end with the command of the program which the microprocessor unit 10 reads from the storage means 11. An up/down counter 5 is added and subtracted based on a comparison result. Thus, the runaway cause of the micro processor unit 10 can be detected based on a calculated result concerned. Then, runaway can be checked without connecting the measurement unit such as the emulator to the microprocessor unit 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor runaway monitoring circuit for monitoring runaway of a microprocessor unit (MPU), and more particularly to a microprocessor runaway monitoring circuit capable of executing and analyzing the cause of MPU runaway.

In recent years, a program for operating an MPU or the like often uses a multiple nest structure. MPU runaway is likely to occur when this multiple nested program is evaluated or executed. Therefore, a runaway monitoring circuit for detecting information for analyzing the cause of this MPU runaway is required.

[0003]

2. Description of the Related Art Conventionally, as a microprocessor runaway monitoring device of this type, a measuring device such as an emulator is connected to an output terminal of an MPU on the monitored side, and based on output data of the MPU output from this output terminal. The MPU detects runaway of the MPU and analyzes the runaway of the MPU by using a trace function of an emulator or the like.

[0004]

Since the conventional microprocessor runaway monitoring device is configured as described above, it is necessary to separately connect the measuring device such as an emulator to the MPU, and the runaway monitoring of the MPU becomes complicated. Had the following problems.

The present invention has been made to solve the above problems, and proposes a microprocessor runaway monitoring circuit capable of monitoring runaway of an MPU without separately connecting a measuring device such as an emulator to the MPU. To aim.

[0006]

FIG. 1 shows the principle of the present invention. In the figure, the microprocessor runaway monitoring circuit according to the present invention is provided with a storage means 1 for storing a program.
In a microprocessor runaway monitoring circuit that monitors a runaway of a microprocessor unit 10 that reads a program from 1 and executes a plurality of commands of the program, indicates a command start in an arbitrary command of the program, and executes the program in advance before the execution of the program. A first data storage unit 1 for storing start reference data to be set, and a second data storage for indicating command end in an arbitrary command of the program and storing end reference data preset before execution of the program If the command of the program read by the microprocessor unit 10 from the storage unit 11 and the start reference data stored in the first data storage unit 1 are compared with each other, the first match signal is output. And a first comparator circuit 3 for outputting The second comparison circuit outputs a second coincidence signal when the command of the program read from the storage unit 11 and the end reference data stored in the second data storage unit 2 are compared with each other and coincide with each other. Up-down operation that performs addition operation when the first match signal of the circuit 4 and the first comparison circuit 3 is input, and subtracts operation when the second match signal of the second comparison circuit 4 is input A counter 5 is provided, and the cause of runaway of the microprocessor unit 10 is monitored based on the calculation result of the up / down counter 5.

[0007]

According to the present invention, reference data of start and end indicating the start and end of a command in the program stored in the storage means to be executed are preset and stored in the first and second data storage sections. The first and second comparison circuits respectively store and store the respective reference data for start and end with the command of the program read from the storage means by the microprocessor unit, and up and down based on the comparison result. Since the addition / subtraction of the counter is performed, the cause of the runaway of the microprocessor unit can be detected based on the calculation result, and the runaway is monitored without separately connecting a measuring device such as an emulator to the microprocessor unit.

[0008]

【Example】

a) One Embodiment of the Present Invention One embodiment of the present invention will be described with reference to FIGS.

The microprocessor runaway monitoring circuit according to this embodiment shown in FIG. 2 is connected to the data bus 10.
Each processing command of the program transmitting 0 is MPU10.
To the first and second latch circuits 1 and 2 which are input to the first and second latch circuits 1 and 2 and are latched. , The second comparison circuits 3 and 4 perform comparison, and the up / down (U / D) counter counts up or down based on the match signals Y ₁ and Y ₂ (inversion) of the comparison result. In this configuration, the MPU 10 is monitored for runaway. The U / D counter 5 has a control circuit 6 connected to each clear terminal, and is configured to clear the count value based on a clear control signal CLR (inversion) output from the control circuit 6. The control circuit 6 sends the system clock signal C to the U / D counter 5.
LK is output and addition or subtraction is performed at the rising timing of the system clock signal CLK.

Next, in the operation of this embodiment based on the above-mentioned structure, the processing operation is divided into areas by call (CALL) and return (RET) (FIG. 3) and write (WR).
The case where the processing operation is divided into areas by the read (RE) processing (FIG. 4) will be described as an example.

The call (CALL) and return (RE)
When the processing operation is divided into regions by T), as shown in FIG.
Command to move to address 100 of subroutine A and execute the process of subroutine A.
, The next instruction of the main program is executed, and the MPU 10 during execution of this multiple nested program is executed.
It monitors the runaway of.

First, from the keyboard 12, the address "50" of the main program, the content "CALL instruction", the address "100" of the subroutine A, and the content "RET instruction" are used as the reference comparison data _Ds1 and _Ds2 for the start and end. The reference comparison data D _s1 and D _s2 of the start and end are set and stored in the memory 11. This is the start reference comparison data D _s1 is applied a first address adr ₁ to identify the latch circuit 1, also the termination criterion comparative data D _s2 is the address adr ₂ is applied to identify the first latch circuit 2 , Are stored in the memory 11.

The address strobe signal is transmitted from the MPU 10.
When the signal ALE is output to the control circuit 6, the time t in FIG.₁
~ T₂Start reference comparison data D_s1A given to
Dress adr₁Is read. Also, time t₂~ T₃To
Then, the write control signal WR (inversion) is input to the control circuit 6.
Then, the control circuit 6 latches the first latch circuit 3
The control signal C (inversion) is output, and the first latch circuit 3
Start criteria comparison data D _s1Latch. As well as this
Interval t₃~ T₆The second latch circuit 3 compares the end criteria
Data D_s2Latch. Here, from the control circuit 6 to U /
Clear signal CLR (inversion) output to D counter 5
Output from U / D counter 5 from undefined state
Set to "0".

When the address strobe signal ALE is output from the MPU 10 to the control circuit 6 in this state, the MPU 1
0 is a command of the program transmitted from the memory 11 via the data bus 100, and is “C” of the main program.
The address adr ₁ associated with the "ALL instruction" is input (Fig. 5
Of time t _{7 to} t ₈ ) and this "CALL instruction" is input to the first comparison circuit 3 as the comparison data D _R1 (see times t _{8 to} t _{9 of} FIG. 5). The first comparison circuit 3 outputs the coincidence signal Y ₁ (inversion) when the address adr ₁ is input during the time t _{7 to} t ₈ . The coincidence signal Y ₁ (inversion) is input to the U / D counter 5 as a count-up signal, the U / D counter 5 counts up from “0” to “1” and outputs the count signal Q (FIG. 5). Time t
See ₈ ). Further, the MPU 10 continues to read the program from the memory 10 and the subroutine A of this program
Address from 100 to 120 and address 12
The address adr ₂ associated with the “RET instruction” of 0 is input to the second comparison circuit 4 (time t _{10 to} t _{11 in} FIG. 5), and the input of this address adr ₂ causes the second comparison circuit 4 to output the match signal Y ₂ ( Inversion) is output. This coincidence signal Y ₂ (inversion) is input to the U / D counter 5 as a countdown signal, and this U / D counter 5 counts down from “1” to “0” and outputs the count signal Q (time in FIG. 5). t
See ₁₁ ).

In this way, since the value of the count signal Q of the U / D counter 5 is output as "0" when the main program is restored, it is assumed that the MPU 10 is operating normally without running away. I can judge.

Further, in FIG. 6, when the MPU 10 runs out of control,
A timing chart is shown, in which the normal
In the case of FIG. 5 unlike the case of FIG. 5 in which the MPU 10 operates
Interval t ₉Address strobe signal from MPU 10
Even though ALE is output to the control circuit, M
The PU10 has the "RET" at the address 120 of the subroutine A.
Address adr associated with instruction₂Input as comparison data
Then, the second comparison circuit 4 outputs the coincidence signal Y₂(Reverse) appears
I can't help. This match signal Y₂(Reverse) is U / D count
The U / D counter 5 does not output to
Count signal with count value "1" without performing down
Q will continue to be output. This makes the MPU
Count where 10 should return to the main program
Since it is the count signal Q with the value "1", the subroutine
It is determined that MPU10 has runaway during A
It will be. In addition, this runaway is a multiple nesting professional
An error occurred in any subroutine in the gram
You can analyze what you did.

A program such as that shown in FIG. 4 may be written in, for example, write commands (WR1 to n) and read commands (RE1 to RE1).
Even when the area is divided by n) or the like, the cause of the runaway can be analyzed as in the case of the subroutine of FIG. In this case, it is possible to analyze whether an error has occurred in any of the processes 1 to n divided into areas by the write command and the read command as shown in FIG.

B) Another Embodiment of the Present Invention Another embodiment of the present invention will be described with reference to FIG. In the figure, a microprocessor runaway monitoring circuit according to another embodiment is similar to the embodiment circuit shown in FIG. 2, and has first and second latch circuits 1 and 2, first and second comparison circuits 3,
4, a U / D counter 5 and a control circuit 6 are provided, and in addition to this configuration, an instruction register 7, a flag register 8 and an n-bit counter 9 are provided.

The instruction register 7 is a data bus 100.
Is connected between the first and second latch circuits 1 and 2,
Only the command contents of the program transmitted on the data bus 100 are stored to store the first and second latch circuits 1,
Output to 2. The n-bit counter 9 sets a flag in the flag register 8 when the counter signal Q of the U / D counter 5 has a count value "1" for several seconds. With this flag, runaway of the MPU 10 can be analyzed.

[0020]

As described above, according to the present invention,
The reference data of the start and end indicating the start and end of the command in the program stored in the storage means to be executed is preset and stored in the first and second data storage units, and the stored start is stored. , The end reference data is compared with the command of the program read from the storage means by the microprocessor unit in the first and second comparison circuits, respectively, and addition / subtraction of the up / down counter is performed based on the comparison result. Therefore, the cause of the runaway of the microprocessor unit can be detected based on the calculation result, and there is an effect that the runaway can be monitored without separately connecting a measuring device such as an emulator to the microprocessor unit.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block configuration diagram of a microprocessor runaway monitoring circuit according to an embodiment of the present invention.

FIG. 3 is a program diagram having a subroutine targeted by the embodiment described in FIG.

FIG. 4 is another program diagram targeted by the embodiment described in FIG.

5 is a timing chart at the time of normal execution of the MPU of the embodiment described in FIG.

FIG. 6 is a timing chart at the time of MPU runaway of the embodiment described in FIG.

FIG. 7 is a block configuration diagram of a microprocessor runaway monitoring circuit according to another embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... 1st latch circuit 2 ... 2nd latch circuit 3 ... 1st comparison circuit 4 ... 2nd comparison circuit 5 ... Up / down (U / D) counter

Claims (1)

[Claims] 1. A storage means (1) for storing a program
1) A microprocessor unit (1) for reading a program from the program and executing a plurality of commands of the program.
In a microprocessor runaway monitoring circuit for monitoring runaway of (0), a first data storage section (1) for indicating a command start in an arbitrary command of the program and storing start reference data set in advance before execution of the program ), A second data storage unit (2) for indicating the end of a command in an arbitrary command of the program, and storing end reference data set in advance before the execution of the program, and the microprocessor unit (10). The command of the program read from the storage means (11) and the first command
A first comparison circuit (3) for outputting a first coincidence signal when the start reference data stored in the data storage section (1) is compared with each other, and the microprocessor unit (10). The program command read from the storage means (11) and the second command
A second comparison circuit (4) that outputs a second match signal when the end reference data stored in the data storage section (2) is compared with each other and a match is found; ), The addition operation is performed when the first match signal is input, and the up-down counter (5) that performs the subtraction operation when the second match signal of the second comparison circuit (4) is input, A microprocessor runaway monitoring circuit for monitoring the cause of runaway of a microprocessor unit (10) based on the calculation result of the up / down counter (5).