JPS63197245A - Microprogram controller - Google Patents

Abstract

PURPOSE:To omit the addition of a debug-only routine by stopping the run of a microprogram in the case of setting an optional register at the prescribed value and then at the target value in the form of a hardware operation while each microinstruction of the microprogram is executed. CONSTITUTION:The run of a microprogram is stopped when an optional register is set at the value designated previously and then at the target value designated separately. In other words, it is supposed that a certain register is usually set at a prescribed value X1 and then at a target value X2. Under such conditions, the abnormality of the microprogram is detected after a considerable period of time passed from occurrence of said abnormality even though the value X1 is not changed to the value X2 due to a program bug, etc., and changed to other value X3. Thus the analysis of the abnormality is sometimes difficult. In such a case, the run of the microprogram is stopped when the value X1 is changed to the value X3 so that the abnormality can be easily analyzed.

Description

TECHNICAL FIELD The present invention relates to a microprogram control device, and more particularly to a microprogram control device having a depacking function.

BACKGROUND OF THE INVENTION In general, microprogram control devices are capable of suspending the execution of a program at any pre-designated address in a control memory where the microprogram is stored, in order to facilitate debugging of the microprogram. It has functions.

That is, 1IllJ111 that generally supplies control memory.
A comparison address register is provided to store address data for comparison with a storage address, and the contents of this comparison address register and 1lJt[
] The control memory address supplied to the memory is compared with the control memory address, and if a match is detected, the execution of the microprogram can be stopped.

When debugging, the 4111m storage address where the microinstruction whose execution of the microprogram should be temporarily stopped is input from, for example, a console, stored in the comparison address register, and then the microprogram is started. Then, when the microphone program stops at this specified instruction (control memory address) due to the above-mentioned function, the processing by the microprogram is completed by checking the contents of various registers and other internal states in this state. Check whether it is working as desired. When this confirmation process is completed, the next address to be stopped is specified again as needed, and the program can be restarted from the current stopped address (or any other arbitrary address). II like this
This function provides a powerful means for debugging.

The above-mentioned conventional microprogram control device has a method for debugging a specific routine under conditions such as when a certain register reaches a specified value and then changes to another specified value. It is possible to stop at a specific routine address if you know whether the condition is met. However, in general, microprograms cannot be predicted because they perform complex operations depending on the order of software instructions or external factors (interrupts from input/output devices, etc.), and in reality, stopping under such conditions is impossible. Can not.

Therefore, in conventional microprogram control devices, if a certain register in a specific routine reaches a specified value and then reaches another specified value, a command is issued to branch to a unique address (or to stop the microprogram). Equivalent functionality is achieved by adding debugging-specific routines such as (execution).

However, the above method is not performed equally at all timings of microprogram execution, and has the disadvantage that a dedicated debugging routine must be added each time where it is considered to be minimally necessary.

An object of the present invention is to provide a microprogram control device that does not require the addition of a debugging routine and is capable of stopping a microprogram equally at all timings of execution of the microprogram.

According to the present invention, a micro-instruction register in an information processing device δ includes a micro-instruction register that stores micro-instructions read from the υill storage unit, and micro-instruction execution means that controls execution according to the micro-instructions. The program control device includes a bus output instruction register that stores a microinstruction for deriving the contents of a predetermined register in the microinstruction execution means to an internal bus, and one of the microinstruction register and the bus output instruction register. a first detection means for detecting that the data on the internal bus matches a predetermined first expected value; , the data on the internal bus is a predetermined second
a second detection means for detecting that the value matches the expected value;
1llt [1 means] for stopping execution of the microinstruction execution means when a match is detected by the second detection means after a match is detected by the first detection means. A program control device is obtained.

Example Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. The microprogram I, 11 control device of this embodiment has a control memory 1. Instruction register 2. Bus output instruction register 31 selection circuit 4. Execution control unit 5. Flip 70 Tsubu (hereinafter referred to as F/
(abbreviated as F)6. Comparison data registers 7 and 8. Comparison circuit 9 and 10° AND gate 11. It has an F/F 12 and AND gates 13 and 14.

Next, the operation of the microprogram control device of this embodiment configured as described above will be explained.

The microprogram stored in the control memory 1 is read into the instruction register 2, selected by the selection circuit 4, and supplied to the execution control section 5 for execution. In this case, F/F6 is logic “
0'', and the selection circuit 4 selects the microinstruction stored in the instruction register 2.The F/F 6 selects the microinstruction stored in the instruction register 2 every clock cycle, that is, the microinstruction is selected. It has a function of inverting the value every time it is executed. Therefore, after the microinstruction in the instruction register 2 is executed by the execution control unit 5, the F/F 6 becomes a logic "1".
'', the selection circuit 4 selects the contents of the bus output instruction register 3, and a microinstruction for outputting an arbitrary register to the internal bus is supplied to the execution υ control unit 5 and executed.

On the other hand, the instruction register 2 is held when the F/F 6 is logic "1", and the microinstruction from the control memory 1 is stored only when the logic is 1401%.

The above operation will be explained with reference to the timing chart shown in FIG. A is supplied and executed. As a result, the microinstruction B to be executed next is read out from the control memory 1 and stored in the instruction register 2. Also,
At the same time, the F/F 6 is inverted to logic "1s," and the execution control section 5 is then supplied with the microinstruction Z stored in the bus output instruction register 3 and executed.

Thereafter, by repeating the same operation, bus output instruction 2 is inserted at the gate of each microinstruction instead of the original execution of A-8-+C of a normal microprogram, and A→z-+8- An execution like +Z→C is realized. However, No. 1, bus output instruction 2 only outputs an arbitrary register to the bus and does not change any hardware state.

Now, the unique function aimed at by the present invention is to stop the execution of a microprogram when an arbitrary register reaches a pre-designated prerequisite value and then reaches a separately designated target value.

That is, for example, assume that for a bond whose value in a certain register has become the prerequisite value x 1, the value has normally become the target value x 2. However, even if due to a bug in the microprogram, the target value is not x2 and instead becomes another value x3, the microprogram will detect the abnormality long after the abnormal operation has been executed, making it difficult to analyze. It often happens. In such a case, after becoming x1, x3
Analysis will be easier if the microprogram is stopped when this happens.

This embodiment deals with such requests as follows.

Prerequisite value x1 and objective 1ix3 are stored in advance in comparison registers 8 and 7, respectively, from a console (not shown). Furthermore, the F/F 12 is also reset to 0''. In this state, the bus output data is sent to the comparison circuits 9 and 10 via the signal line 105 every time the microprogram is executed.
and are compared with data in comparison data registers 7 and 8, respectively. Comparing circuits 9 and 10 output 1'' when the bus output data and the respective comparison data match.

The output of the comparator circuit 10 is further processed by an AND gate 11 as F/
By performing a logical AND process with F6, F/F12 stores that the bus output by bus output command Z, that is, the specified register has become the target [x3. The output of the comparator circuit 9 is logically ANDed with F/F12 by the AND gate 13, and also roughly logically ANDed with F/F6, so that the output is connected to the signal line 1.
14, "1'' is output only when the specified register becomes the target value x 3 after becoming the prerequisite value x 1. The signal line 114 is used as the microprogram stop factor signal for execution a, II. It is supplied to the control section 5.

With the above operation, the microprogram can be stopped as desired when the specified register reaches the target value x3 after the prerequisite value x1.

It is assumed that the bus output instruction register 3 is supplied with a microinstruction 'i'I instructing the bus output of the comparison target register from the console in advance and stored therein.

As explained above, according to the present invention, when an arbitrary register reaches a predetermined predetermined value and then becomes a target value as a hardware operation during the execution of each microinstruction of a microprogram, By stopping the microprogram, it is not necessary to add a conventional debugging routine, and it also becomes possible to provide a powerful debugging method that can equally stop the microprogram at all timings of microprogram execution, improving debugging efficiency. This has the effect of achieving

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a time chart showing the operation of the blocks in FIG. Explanation of numbers for main parts 1...tiI1wJ storage section 2...Instruction register 3...Bus output instruction register 4...Selection circuit 5... ...Execution control section

Claims (1)

[Claims] A microprogram control device for an information processing device, comprising a microinstruction register that stores microinstructions read from a control storage unit, and microinstruction execution means that controls execution according to the microinstructions, the microinstruction execution means a bus output instruction register for storing a microinstruction for deriving the contents of a predetermined register in the means to an internal bus; and the microinstruction execution means by alternately selecting one of the microinstruction register and the bus output instruction register. a first detection means for detecting that the data on the internal bus matches a predetermined first expected value; a second detection means for detecting a match with a second expected value; and a second detection means for detecting a match with a second expected value; A microprogram control device comprising: control means for stopping execution of the execution means.