JPS62111336A - Debugging system - Google Patents

Abstract

PURPOSE:To easily debug in a sequence having complex conditions by comparing various data obtained from a data processor previously prepared comparing data, successively updating the comparing data every coincidence of both the data, when the inputted data coincide with the final comparing data, stopping an software instruction. CONSTITUTION:Data indicated by a selection code from a storage circuit 12 are selected out of an operand address value, a microinstruction address and a software instruction code inputted from the data processor 11 to a selecting circuit 13 and the selected data are compared with comparing data obtained from the storage circuit 12 by a comparator 14. If a control bit for the storage circuit 12 does not indicate the final word by a control circuit 15 to which a coincidence signal has been inputted, an updating signal is outputted so as to indicate the succeeding word to a register 17. When the control bit is the final word, the stop of the software instruction is indicated to an instruction control circuit 18.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a debugging method, and more particularly to a software debugging method in a data processing device.

[Conventional technology]

The conventional debugging method is
・Various tracing methods have been considered to collect data when debugging software. For example, by detecting an instruction address match and placing the instruction in a halt state after the instruction completes, internal data up to that point can be collected. However, as shown in Figure 5, when there are A to F instructions and data is collected after execution with D instruction, A-B-C
Even when attempting to collect data when executed as -+D, data obtained when executed as A-E-C-D or F'-D is sometimes collected and cannot be distinguished.

[Problem that the invention seeks to solve]

The conventional debugging method described above has the drawback that it is not possible to specify the instruction sequence, microprogram sequence, hardware conditions, etc. for reaching the software instruction of the comparison address. [Means for Solving the Problems] The debugging method of the present invention includes a data processing device controlled by a microprogram, a plurality of types of comparison data, a code indicating the type of comparison data, and a code indicating that the comparison data is the last one. a storage means for storing a plurality of types of internal data sent from the data processing device, and a storage means for storing a plurality of types of internal data sent from the data processing device; A selection means for selectively outputting internal data and a comparison means for comparing the output of the selection means with the contents of the designated read position of the storage means.If the comparison results match, whether or not the comparison data is the last data. If it is not the last comparison data, it instructs to read the next read position of the storage means, and selects the internal data from the selection means indicated by the read code and the read comparison data. a control circuit that continues comparison with the data and outputs a sequence check signal when the bit indicates the last comparison data; and an instruction control circuit that causes the sequence check signal to cause the instruction to be stopped after the software instruction currently being executed is completed. It has a circuit.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the invention. In FIG. 1, the present embodiment has a data processing device 11 and a storage circuit 12. This data processing device 11 is controlled by a microprogram, and the sequence of operand access address values microprograms used according to this control is controlled by a microprogram. It is configured to send out a microinstruction address and an instruction code of a software instruction. The storage circuit 12 stores a selection code indicating which of the three types of data sent from the data processing device 11 is to be compared, and comparison data for comparison.
The selection code is sent to the selection circuit 13, and the comparison data is sent to the comparison circuit 1.
It is connected so that it is sent to 4. Furthermore, the memory circuit 12
Each word is provided with a control bit indicating whether the selection code and comparison data of that word is the last data, and the output thereof is sent to the control circuit 15. Selection circuit 14
inputs three types of data sent from the data processing device 11: an operand address value, a microinstruction address, and a software instruction code, selects and outputs the data indicated by the selection code of the storage circuit 12, and sends it to the comparison circuit 14. Comparison circuit 14 is connected to selection circuit 13 and memory port i\81
Input and compare the comparison data of 2, output the comparison result,
The signal is sent to the control circuit 15. The control circuit 15 is the comparison circuit 14
When a match signal is sent from the memory circuit 12, if the control bit of the memory circuit 12 does not indicate the last word, it outputs an update signal to the register 17 to indicate the next word. It shows that
The instruction control circuit 18 is instructed to stop the software 1 from issuing the software instruction, and a clear instruction is issued to the register 17 so that the first word of the storage circuit 12 is indicated. The decoder 6 decodes the microinstruction of the data processing device 11 and issues a clearing instruction to the register 17 when the microinstruction for clearing the register 17 is executed. register 17
stores an address indicating a word in the memory circuit 12 and is controlled by a decoder 16 and a control circuit 15. The instruction control circuit 18 is configured to control the instruction signal from the control circuit 15 to stop the instruction after the software instruction currently being executed is completed.

Next, the operation of one embodiment of this embodiment will be explained step by step using three processing examples as shown in FIG. 2. Here, we will consider the case where the conditions of the place where the clock is stopped are as follows. Software instructions appear in the order of A instruction → B instruction, and the B instruction accesses the operand at address C.f! When the microinstruction address at address &83 is executed, the trace operation of the tracer 18 is stopped. At this time, the memory circuit 12 stores the data shown in FIG.
Store in advance. The selection code and control bit each have a meaning as shown in FIG.
0"" indicates the microinstruction address, furthermore, the control bit "0" indicates a word other than the final word, and the control bit "1" indicates the microinstruction address.
indicates the final word.

In the sequence shown in Fig. 2 (a>, instructions A-D-E→B
shows the sequence of software instructions, and Fig. 2(b)
In the sequence, instruction B, -B2→B, indicates a microinstruction sequence in the B instruction.

When the A instruction is executed, the data processing device 11 outputs the software instruction code ° “A” and the selection circuit 13
is input. The selection code "'o o" and the comparison data "A°" stored in the first word are outputted from the storage circuit 12 and input to the comparison circuit 14 together with the data data "A°" outputted from the selection circuit 13.

Comparison circuit 14 sends a match signal to control circuit 15, which in turn sends an update signal to register 17 to indicate the next word.

Next, when the D instruction is executed, the software instruction code °°D' is output from the data processing device 11 and inputted to the comparison circuit 14 along with the comparison data 'B' sent from the storage circuit 12 through the same path as described above. Ru. At this time, the comparison result does not match, and the control circuit 15 and register 17 do not operate.The same is true for the 9th order l instruction.

When the B instruction is further executed, the comparison circuit 14 again sends out a match signal, the control circuit 15 updates the register 7, and outputs the next word of data.

Processing progresses in this way and microinstructions A and I in the B instruction are
A match of operand address == CI+ is detected at address B2, and a match of microinstruction address ゛B3゛° is detected at address B3. At this time, the control pitch I of the word output from the memory circuit 12 is ゛1°'. Therefore, the control circuit 15 issues an instruction to the instruction control circuit 18 to stop the software instruction. In response to this instruction, the instruction control circuit 18 places the instruction in an instruction halt state after the currently executed instruction is completed. As a result, the internal data of the data processing device 11 up to the time when the command is stopped can be collected using the maintenance function or the like provided in the data processing device 11. Further, by providing the instruction control circuit 18 with a function of executing one instruction or restarting an instruction, a more detailed investigation can be performed.

Even in such a complicated sequence of conditions, by storing data that satisfies the conditions in the memory circuit 12, it becomes possible to easily select and obtain data necessary for debugging.

〔Effect of the invention〕

As explained above, the present invention uses a data processing device to compare obtained various data with comparison data prepared in advance, update the comparison data sequentially each time there is a match, and detect a match with the last comparison data. This has the effect of making it easier to debug sequences with complex conditions by stopping the software instructions when the software instructions occur.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing a software instruction flow and a microinstruction flow for explaining the operation of the present invention, and FIG. 3 is a diagram showing a diagram of a memory circuit in this embodiment. v) - A diagram showing the configuration; FIG. 4 is a diagram showing the contents of the selection code and control bits in FIG. 3;
The figure is a diagram showing the flow of instructions used to explain the prior art.

Claims (1)

[Claims] a data processing device controlled by a microprogram; a storage means for storing a plurality of types of comparison data; a code indicating the type of the comparison data; and a bit indicating whether the comparison data is the last data; a selection means for inputting a plurality of types of internal data and selectively outputting the internal data indicated by a code indicating the type of comparison data sent from the storage means; and an output of the selection means and a designated reading position of the storage means. and a comparison means for comparing the contents of the storage means, and when the comparison results match, a bit indicating whether or not the comparison data is the last data is determined, and if it is not the last comparison data, reading of the next read position of the storage means is performed. and continues comparing the internal data from the selection means indicated by the read code with the read comparison data, and outputs a sequence check signal if the bit indicates the last comparison data. A debugging method comprising: a control circuit; and an instruction control circuit that uses the sequence check signal to bring an instruction to a halt state after the currently executed software instruction ends.