JPS6231444A - Pseudo fault generating system - Google Patents

Abstract

PURPOSE:To facilitate an easy pseudo test under complicated conditions by comparing a data given from a data processor with a comparison data and producing a pseudo fault when the final coincidence is obtained with the comparison data. CONSTITUTION:A selection circuit 3 is controlled by the selection code 21 of a memory 2 and the sequential data are selected from a data processor 1. These selected data are compared with the corresponding comparison data of the memory 2 through a comparator 4. The comparison data 22 is replaced with the coincidence output given from the comparator 4 and via a control circuit 5, a register 7 storing the output of a decoder 6, etc. Then a pseudo fault generating circuit 8 is started by the final coincidence output via the circuit 5. Thus the pseudo fault is produced without using a microinstruction and a pseudo fault test is carried out through the processor 1. This facilitates an easy pseudo test under the complicated conditions.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD The present invention relates to a method for generating a pseudo failure in a data processing device.

Wataru I. Conventionally, in data processing devices, there is a method of generating a pseudo failure to perform failure handling when evaluating hardware failure handling. As a means of generating such a failure, there has been a method of generating a pseudo failure using a microinstruction.

According to this method, a microinstruction that causes a pseudo fault is embedded in a microinstruction of an arbitrary step in a microprogram, and when that step is executed while the data processing device is operating, a pseudo fault occurs and the fault processing is not performed. It was something that would happen. However, this method has the disadvantage that it is not possible to specify the software instruction sequence, microprogram sequence, other hardware conditions, etc. up to that step.

OBJECT OF THE INVENTION The object of the present invention is to specify the software instruction sequence, microprogram sequence, and other hardware conditions leading up to the occurrence of a pseudo failure;
An object of the present invention is to provide a method for generating a simulated failure that allows a simulated failure test to be easily performed even under complicated conditions.

Structure of the Invention The pseudo-fault generation method according to the present invention is a pseudo-fault generation method for evaluating hardware fault processing in a data processing device controlled by a microprogram. The data storage means stored in a predetermined order and the various data derived from the data processing device are compared with the data derived from the data storage means, and each time the two match, the data derived from the data storage means is The present invention is characterized in that a pseudo failure is generated when a match is detected between the last comparison data.

Example Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the invention.

The data processing device 1 is controlled by a microprogram and is configured to send operand access address values used in accordance with the control, microinstruction addresses indicating the sequence of the microprogram, and instruction codes of software instructions.

The storage circuit 2 stores comparison data 22 sent from the data processing device 1, the selection code 21 is sent to the selection circuit 3, and the comparison data 22 is sent to the comparison circuit 4, respectively. Further, each word of the memory circuit 2 is provided with a control bit 23 indicating whether the selection code and comparison data of that word are the last data, and the output thereof is sent to the control circuit 5.

The selection circuit 3 inputs three types of data: the operand address value, microinstruction address, and software instruction code selected from the data processing device 1, selects and outputs the data indicated by the selection code of the storage circuit 2, and outputs the selected data to the comparison circuit 4.
Send to. The comparison circuit 4 is connected to the selection circuit 3 and the storage circuit 2.
The comparison data is inputted and compared, and the comparison result is output and sent to the control circuit 5.

When the control circuit 5 receives the match signal from the comparison circuit 4, if the control bit of the storage circuit 2 does not indicate the final word, it outputs an update signal to the register 7 to indicate the next word. Furthermore, if the control bit indicates that it is the final word, the pseudo fault generation circuit 8 is notified of the pseudo fault (
In addition to issuing an instruction to cause a pseudo fault), register 7
A clear instruction is issued to indicate the first word of the memory circuit 2.

The decoder 6 decodes the microinstruction of the data processing device 1, and issues a clear instruction to the register 7 when the microinstruction for clearing the register 7 is executed. register 7
stores the address indicating the word of the memory circuit 2, and the decoder 6
and is controlled by the control circuit 5.

The pseudo-failure generation circuit 8 sets an error flag in the data processing device in response to an instruction signal from the control circuit 5, and generates a pseudo-fault. When the error flag is set, failure handling originally provided in the data processing device is executed.

Next, the operation of the present invention will be explained step by step using the process shown in FIG. 2 as an example. Let us now consider the following conditions for causing a false failure. It is assumed that software instructions appear in the order of instructions A to B, and a false failure occurs when the microinstruction address at address 83 is executed after the B instruction accesses the operand at address C. At this time, it is assumed that data as shown in FIG. 3 is stored in the memory circuit 2 in advance. The meanings of the selection code 21 and control bit 23 in FIG. 3 are as shown in FIGS. 4(A) and 4(B), respectively.

In the sequence of FIG. 2, A-D→E-)B indicates a software instruction sequence, and B1→B2→B3 indicates a microinstruction sequence in the B instruction.

When the A instruction is executed, the data processing device 1 outputs the software instruction code "A" and inputs it to the selection circuit 3.The storage circuit 2 outputs the selection code ++ 00 u and stored in the first word. Comparison data "A'' is output and inputted to comparison circuit 4 together with data "A" output from selection circuit 3. The comparison circuit 4 sends a match signal to the control circuit 5, which in turn sends an update signal to the register 7 to indicate the next word.

Next, when the D instruction is executed, the software instruction code "D11" is output from the data processing device 1, and is input to the comparison circuit 4 through the same bus as described above together with the comparison data "B" sent from the storage circuit 2. be done. Therefore, at this time, the comparison result does not match, and the control circuit 5 and register 7 do not operate. The same applies to the next E command.

When the B instruction is further executed, the comparison circuit 4 again sends out a match signal, the control circuit 5 updates the register 7, and the next word of data is output.

Processing progresses in this way, and the operand address ""C" matches at the microinstruction address B2 in the B instruction, and furthermore, the microinstruction address "'13" matches at the address B3.
A 3°' match is detected. At this time, the control bit of the word output from the memory circuit 2 is 1'', so the control circuit 5 issues a pseudo fault generation instruction to the pseudo fault generation circuit 8. The pseudo fault generation circuit 8 receives this instruction. The error flag of the data processing device 1 is set and a false failure occurs.

In this way, by storing data that satisfies the conditions in the memory circuit 2, false failures can be generated freely under such complicated conditions.

°As described in detail, according to the present invention, various data obtained from a data processing device are compared with comparison data prepared in advance, and each time the two match, the comparison data is sequentially updated, and after R. By generating a pseudo fault when a match is detected with the comparison data, it is possible to easily perform a pseudo fault test under complex conditions.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram showing a software instruction flow and a microinstruction flow for explaining the operation of the present invention, and FIG. 3 is a memory circuit 3 of FIG.
FIG. 4 (A>, (B) is a diagram showing the contents of the selection code and control bit in FIG. 3, respectively. Explanation of symbols of main parts 1... Data Processing device 2... Memory circuit 3... Selection circuit 4... Comparison circuit 5... Control circuit 6... Decoder 7... ···register

Claims (1)

[Claims] A pseudo failure generation method for evaluating hardware failure processing in a data processing device controlled by a microprogram, the data storage means storing various data used under the control of the microprogram in advance based on a predetermined order. and means for comparing various data derived from the data processing device with data derived from the data storage means, and each time the two match, sequentially updating and deriving the data derived from the data storage means. , a pseudo failure generation method is characterized in that a pseudo failure is generated when a match is detected between the last comparison data.