JPS6320547A - Data processor - Google Patents

Abstract

PURPOSE:To easily analyze a fault of a table data, which has been complicated intricately, by collating an address data inputted from a table address register at the time of updating a table memory, with an address which has been stored separately. CONSTITUTION:For instance, in case a part of an address A has been broken down, when the address A is set to a table address register 12, an address collating circuit 14 is brought to an access, and if the address A is set in advance in the address collating circuit 14, the address collating circuit 14 outputs an updating signal (e). In this state, when a data in a table memory 11 is updated, an updating flag is set in an updating flag circuit 15 and it is reported to other device by an attention signal (f). With this as a turning point, the contents of a control table are read out and saved. In the same way, with regard to addresses B, C, as well, the contents of the control table are read out and saved. In this way, a state of the control table at the time when the control table has been updated in accordance with each of the addresses A, B and C can be read out.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a data processing device that has a microprogram and a control table and performs control by updating and referencing the control table, and in particular, relates to a data processing device that has a microprogram and a control table and performs control by updating and referencing the control table. The present invention relates to a data processing device that can grasp the update status of a target location in a control table in real time and easily perform failure analysis regarding failures caused by complex destruction of the control table.

〔overview〕

The present invention provides a data processing device that has a microprogram and a control table and performs control by updating and referencing the control table, in which address data of the control table stored in the control table memory is arbitrarily verified. By storing the data in the circuit, comparing it with the address data output from the table address register when updating the control table, and updating the control table in the event of a loss, even if a specific address area of the control table is Even if the control table has been destroyed, the control table can be updated correctly, and failures due to control table destruction can be easily analyzed.

[Conventional technology]

Conventionally, this type of device saves the contents of a control table when a failure is detected and performs analysis based on it.

However, in the case of failures caused by destruction or destruction of the control table, if the destroyed part is affected by destruction elsewhere, it is difficult to analyze and it will take a lot of time to find the cause.

FIG. 2 is a block diagram showing such a conventional data processing device. A table memory 1 that stores a control table input from data bus b', a table address register 2 that outputs address data a' for accessing table memory 1 to table memory 1, and controls writing to table memory 1. and a table write control circuit 3 for outputting a write signal C' to the table memory 1.

Now, addresses A and B of the control table are destroyed,
As a result, if a failure occurred that also destroyed address C, it would be extremely difficult to determine the causal relationship between the destruction of the contents of addresses A and B even if the contents of the control table were investigated at the time the failure occurred. be. Furthermore, unless destruction at addresses A and B directly causes a failure, it is difficult to grasp the timing and analyze the control table.

[Problem that the invention seeks to solve]

The conventional data processing device described above can only check the control table when a failure occurs, and is not given an opportunity to check for destruction of the control table that does not directly result in a failure, and it takes a lot of time to find the cause. There was a drawback that it took a while.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data processing device that can easily analyze complex failures caused by control table destruction by eliminating the above-mentioned drawbacks.

[Means for solving problems]

The present invention provides a data processing device including a microprogram and a control table, and a table control means for updating and referencing the control table to perform control, wherein the table control means stores the control table. a table memory; an address verification circuit that stores arbitrary address data in the control table; collates the address data with the address data supplied to the table memory; and outputs an update signal when they match; the table memory and the address verification circuit; a table address register that supplies an address to the table; a write control circuit that outputs a table write signal and an address write signal that control writing of data to the table memory and the address verification circuit; The present invention is characterized by comprising an update flag circuit that generates and outputs an update flag based on input of the signal and the update signal.

[Effect]

The present invention involves fetching and storing address data of a control table to be investigated at any time into an address verification circuit (including a random access memory) from a data bus in response to an address write control signal from a write control circuit; It compares the address data input from the register, and if they match, generates an update signal and outputs it to the update flag circuit. The update flag circuit generates an update flag by inputting this update signal and the table write signal from the write control circuit, and outputs it to other devices as an attention signal. At the same time, the table memory takes in the control table corresponding to the address data from the data bus and updates it.

Therefore, in the present invention, even if the area corresponding to a specific address in the control table is destroyed,
Updates can be performed correctly, and failures due to control table destruction can be easily analyzed.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the main parts of an embodiment of the present invention.

This embodiment includes a table memory 11 which is connected to data bus b and receives and stores a control table from data bus b, and an address which is connected to data bus b and stores address data of the control table and is supplied to the table memory. an address verification circuit 14 that performs verification with the data and outputs an update signal when they match; a table address register 12 that outputs the address data a of the control table to the address memo January 1 and the address verification circuit; A table write signal C that controls writing of the control table to the memory 11, and an address write signal d that controls writing of address data to the address verification circuit 14.
A write control circuit 13 that outputs a table write signal C from this write control circuit and an update signal e from an address matching circuit 14 are input to generate an update flag and send it to other devices as a caution signal f. The update flag circuit 15 includes an update flag circuit 15.

The feature of the present invention is that in FIG. 1, a write control circuit 14,
This is because an address verification circuit 15 and an update flag circuit 16 are provided.

Next, the operation of this embodiment will be explained. Now, if addresses A and B in the control table are destroyed and a failure occurs due to address C, the address matching circuit 14 is sent to address A, B, C or a specific area containing A, B, C. Then, a reproduction test will be performed. First, if address A is destroyed, when address A is written to the table address register 12, the address verification circuit 14 is accessed, and the address verification circuit 1
If the address A is located at 4, the address verification circuit 14 outputs an update signal e. When data is updated in the table memory 11, an update flag is set in the update flag circuit 15 and reported to other devices by an attention signal f. Taking this as an opportunity, the contents of the control table are read out and saved.

Next, when address B is set in the table address register 2, the address verification circuit 14 is accessed, and if address B is set in the address verification circuit 14,
The address verification circuit 14 outputs an update signal e. Here, when data is updated in the table memory 11, an update flag is set in the update flag circuit 15, and is reported to other devices by an attention signal f. Taking this as an opportunity, the contents of the control table are read out and saved.

Similarly, the contents of the control table for address C are read out and saved. This allows addresses A, B, C
It is possible to successively display the state of the control table when the control table is updated corresponding to each of the following.

〔Effect of the invention〕

As described above, the present invention is capable of analyzing the process of updating a control table by comparing the address data output from the table address register when updating the table memory with separately stored address data. This has the effect of making it easier to analyze problems in complex table data.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the main parts of an embodiment of the present invention. FIG. 2 is a block diagram showing the main parts of a conventional example. 1.11...Table memory, 2.12...Table address register, 3...Table write control circuit, 13...Write control circuit, 14...Address verification circuit, 15...Update Flag circuit, a, a'... address data, b, b'... data bus, c, c'...
Data write signal, d...address write signal, e...
Update signal, f...attention signal. Patent distributor: NEC Corporation - Representative: Patent attorney Naotaka Ide.・、-′shilight 1 Fig. conventional example irises 2 mouth

Claims (1)

[Claims] (1) It has a microprogram and a control table,
In a data processing device equipped with a table control means that performs control by updating and referencing the control table, the table control means includes a table memory (11) that stores the control table, and arbitrary address data of the control table. an address matching circuit (14) which stores the address data and matches it with the address data supplied to the table memory and outputs an update signal if they match; and a table address which supplies addresses to the table memory and the address matching circuit. Register (12
), a write control circuit (13) that outputs a table write signal and an address write signal that control writing of data to the table memory and the address verification circuit; A data processing device comprising: an update flag circuit (15) that generates and outputs an update flag based on an input of the update flag circuit (15).