JPS6039253A - Program test device - Google Patents

Program test device

Info

Publication number
JPS6039253A
JPS6039253A JP58147602A JP14760283A JPS6039253A JP S6039253 A JPS6039253 A JP S6039253A JP 58147602 A JP58147602 A JP 58147602A JP 14760283 A JP14760283 A JP 14760283A JP S6039253 A JPS6039253 A JP S6039253A
Authority
JP
Japan
Prior art keywords
circuit
range
contents
register
registers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58147602A
Other languages
Japanese (ja)
Inventor
Kazushi Iwahashi
岩橋 一志
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP58147602A priority Critical patent/JPS6039253A/en
Publication of JPS6039253A publication Critical patent/JPS6039253A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/36Preventing errors by testing or debugging software
    • G06F11/3668Software testing
    • G06F11/3672Test management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To detect accurately a cause of an abnormality with simple constitution and to attain ease of program test by designating a range of addresses where an error is generated and its data range. CONSTITUTION:The range of addresses generating an abnormality is set to an address setting circuit 5 of a program test device and a permissible upper limit value and lower limit value of data registers 3a-3n of a computer 1 are set to a comparison data range setting circuit 6. The value of a counter 2 is read by the 1st register circuit 7 at each write instruction to the registers 3a-3n in synchronizing with the updating of the program counter 2 of the computer 1, and the value of the registers 3a-3n being the range of the address set by the circuit 5 is read in the 2nd register circuit 8 synchonizingly. The contents of the circuit 8 and the permissible value set to the circuit 6 are compared by a comparator circuit 6. The contents of the counter 2 stored in the circuit 7 and the contents of the registers 3a-3n stored in the circuit 8 are displayed on a display circuit 10 depending on the result of comparison of the circuit 9 to ease of the program test.

Description

【発明の詳細な説明】 この発明は、プログラムのテスト装置に関する。[Detailed description of the invention] The present invention relates to a program testing device.

プログラムでは、メモリ内の予定外の情報の発生によっ
て様々な障害を起こす場合が多く存在する。そこで異常
内容がどこで書込まれたのかその原因を知ることが重要
なこととなる。従来は、プログラムの一命令実行毎に実
行結果を出力するトレース機能あるいは特定番地の命令
を実行したときに、実行結果を出力するスナップショッ
トダンプ機能などをプログラムとして組込んで使用して
いたが、確実に意図したデータの変化時期を知ることが
できない欠点がある。また被テストプログラムに変更を
必要とする場合もある。
In programs, various failures often occur due to the occurrence of unexpected information in memory. Therefore, it is important to know where the abnormal content was written and the cause thereof. Conventionally, a trace function that outputs the execution result every time a program instruction is executed, or a snapshot dump function that outputs the execution result when an instruction at a specific address is executed, etc., were incorporated into the program and used. There is a drawback that it is not possible to know with certainty when the intended data changes. Additionally, changes may be required to the program under test.

この発明はかかる欠点を除去し、異常が発生したアドレ
スの範囲とそのデータの範囲を指定することにより、簡
単に確実に、異常の原因を知ることができるハードウェ
アによるプログラムのテスト装置を提供するものである
The present invention eliminates such drawbacks and provides a hardware-based program testing device that can easily and reliably determine the cause of an abnormality by specifying the range of addresses where the abnormality occurs and the range of its data. It is something.

以下図により、この発明の実施例を詳細に説明する。Embodiments of the present invention will be described in detail below with reference to the drawings.

図はこの発明の一実施例を示すブロック図であり、(1
)はテストするプログラムがロードされているマイクロ
プログラム化された計算機、+2+は計算機内のプログ
ラムカウンタ、(5a) 、 (5b)・・・(3旬は
計算機内のデータ1ノジスタ、(4)は計算機内のアド
レスレジスタ、(5)は参照すべき計算機内のメモリの
アドレスの範囲を設定するためのアドレス設定回路、(
6)は比較データ値の範囲を設定するための比較データ
範囲設定回路、(7)はプログラムカウンタの内容を読
込み保持するためのレジスタ回路。
The figure is a block diagram showing one embodiment of the present invention.
) is the microprogrammed computer loaded with the program to be tested, +2+ is the program counter in the computer, (5a), (5b)... (3 is the data 1 register in the computer, (4) is The address register in the computer (5) is an address setting circuit for setting the address range of the memory in the computer to be referenced.
6) is a comparison data range setting circuit for setting the range of comparison data values, and (7) is a register circuit for reading and holding the contents of the program counter.

(8)はアドレス設定回路(5)で設定された範囲のア
ドレスに対応する計算機内のデータレジスタ(3a) 
(8) is a data register (3a) in the computer that corresponds to the address range set by the address setting circuit (5).
.

(6b)・・・(3,、)の内容を格納するレジスタ回
路、(9)はデータレジスタ(5a) 、(5b)・・
・6→の内容が比較データ設定回路で設定された範囲に
あるかをチェックする比較回路、 QQはプログラムカ
ウンタ及びデータレジスタの内容を表示するための表示
回路。
(6b)...A register circuit that stores the contents of (3,,), (9) is a data register (5a), (5b)...
・A comparison circuit that checks whether the contents of 6→ are within the range set by the comparison data setting circuit.QQ is a display circuit that displays the contents of the program counter and data register.

(11a)、 (11b)は比較データ範囲の許容上限
値、許容下限値を示すレジスタ、 (12a)、 (1
2b)・・・(12房はデータレジスタ(3a)、(5
b)・・・G→の内容を保持するレジスタである1゜ このような構成において、まずアドレス設定回路(5)
により異常が発生したアドレスの範囲を設定し、当該ア
ドレスの範囲のメモリの内容の許容上限値及び下限値を
比較データ範囲設定回路(6)で設定する。一方針算機
(1)のプログラムカウンタ12)の更新に同期してメ
モリへの書込み命令毎に計算機(1)からプログラムカ
ウンタ(2)の値を第1のレジスタ回路(7)により読
込み、また前記アドレス設定回路(5)で設定されたア
ドレスの範囲の内容を示すデータレジスタea)、(5
b)・・・(3→の値を前記プログラムカウンタの読込
みに同期して第2のレジスタ回路(8)によりレジスタ
(12a)、 (12b)・・・(12旬に読込む。
(11a), (11b) are registers indicating the allowable upper limit value and allowable lower limit value of the comparison data range; (12a), (1
2b)...(12 cells are data registers (3a), (5
b)...1゜ which is a register that holds the contents of G→ In such a configuration, first, the address setting circuit (5)
A range of addresses in which an abnormality has occurred is set, and a comparison data range setting circuit (6) sets the permissible upper and lower limits of the contents of the memory in the range of addresses. On the other hand, the value of the program counter (2) is read from the calculator (1) by the first register circuit (7) for each write instruction to the memory in synchronization with the update of the program counter (12) of the hand counter (1). data registers ea), (5) indicating the contents of the address range set by the address setting circuit (5);
b)...(3→) is read in the registers (12a), (12b)...(12) by the second register circuit (8) in synchronization with the reading of the program counter.

そして(12a)、 (12b)・・・(12旬の各々
の値と、前記比較 。
And (12a), (12b)... (each value of December and the above comparison).

データ範囲設定回路(6)で設定された許容上限値を示
すレジスタ(11a)と許容下限値を示すレジスタ01
すとを比較回路(9)で比較する。もしレジスタ(12
a)。
Register (11a) indicating the allowable upper limit value set by the data range setting circuit (6) and register 01 indicating the allowable lower limit value
and the comparison circuit (9). If register (12
a).

(121))・・・(12rf)各々の値がレジスタ(
11a)の内容より大きいか又はレジスタ(11b)の
内容より小さい場合には比較回路(9)からの制御信号
により第1のレジスタ回路(7)に保持されたプログラ
ムカウンタ(21の内容及び第2のレジスタ回路(8)
により保持されたデータレジスタ(5a)、 (!+b
)・・・(6n)の内容を表示回路σ0を通して表示す
る。
(121))...(12rf) Each value is in the register (
11a) or smaller than the contents of the register (11b), the program counter (21) held in the first register circuit (7) and the second Register circuit (8)
Data register (5a) held by (!+b
)...The contents of (6n) are displayed through the display circuit σ0.

なおマイクロプログラム化された計算機(1)において
はマイクロプログラムによりアドレスレジスタ(4)で
示されるアドレスからそのアドレス+(n−1)の内容
がメモリへの書込み命令毎にデータレジスタ(5a)、
(5b)・・・(3n)に常に格納されている。
In addition, in the microprogrammed computer (1), the microprogram writes the contents of the address + (n-1) from the address indicated by the address register (4) to the data register (5a) for each write instruction to the memory.
(5b)...(3n) are always stored.

以上のようにこの発明によれば指定した計算機内のメモ
リの値が所定の範囲外の異常値となったとぎ、特に無作
為のアドレスのプログラムが破壊されたとき、どこのプ
ログラムで書込んだかを容易に知ることができ、プログ
ラムをテストする場合に有効である。
As described above, according to the present invention, when the value of the specified memory in the computer becomes an abnormal value outside the predetermined range, especially when the program at a random address is destroyed, it is difficult to determine which program was used to write the data. can be easily known and is effective when testing programs.

【図面の簡単な説明】[Brief explanation of the drawing]

図は9本発明にかかるプログラムテスト装置の一実施例
を示すブロック図であり9図中、(1)は計X機、+2
1は計算機内のプログラムカウンタ、(5a)。 (6b)・・・6嘘ま計算機内のデータレジスタ、(4
)は計算機内のアドレスレジスタ、(5)はアドレス設
定回路。 (6)は比較データ範囲設定回路、(7)は第1のレジ
スタ回路、(8)は第2のレジスタ回路、(9)は比較
回路。 Q(Iは表示回路、(11a) (1l b)はレジス
タ、 (12a)、(12b)・・・(12n)はレジ
スタである。
Figure 9 is a block diagram showing an embodiment of the program test device according to the present invention.
1 is a program counter in the computer (5a). (6b)...6 Data register in the Uma calculator, (4
) is the address register in the computer, and (5) is the address setting circuit. (6) is a comparison data range setting circuit, (7) is a first register circuit, (8) is a second register circuit, and (9) is a comparison circuit. Q (I is a display circuit, (11a) (1l b) are registers, (12a), (12b)... (12n) are registers.

Claims (1)

【特許請求の範囲】 計算機内のメモリ内の内容を取り出すべくアドレスの範
囲を設定するためのアドレス設定回路と。 前記アドレス設定回路で設定した計算機内のメモリの内
容及び計算機内のプログラムカウンタをメモリへの書込
み命令毎に読取りその内容を格納する手段と、読取った
メモリの内容をチェックするための許容上限値及び許容
下限値を設定する比較データ範囲設定回路と、読取った
メモリの内容が前記設定による許容上限値及び許容下限
値の範囲を満足するかを比較する比較回路とを備えたこ
とを特徴とするプログラムテスト装置。
[Claims:] An address setting circuit for setting an address range to retrieve contents in a memory in a computer. Means for reading and storing the contents of the memory in the computer set by the address setting circuit and the program counter in the computer for each write command to the memory, and a permissible upper limit value for checking the read contents of the memory; A program comprising: a comparison data range setting circuit for setting a permissible lower limit value; and a comparison circuit for comparing whether the read contents of the memory satisfy the range of the permissible upper limit value and the permissible lower limit value according to the setting. Test equipment.
JP58147602A 1983-08-12 1983-08-12 Program test device Pending JPS6039253A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58147602A JPS6039253A (en) 1983-08-12 1983-08-12 Program test device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58147602A JPS6039253A (en) 1983-08-12 1983-08-12 Program test device

Publications (1)

Publication Number Publication Date
JPS6039253A true JPS6039253A (en) 1985-03-01

Family

ID=15434042

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58147602A Pending JPS6039253A (en) 1983-08-12 1983-08-12 Program test device

Country Status (1)

Country Link
JP (1) JPS6039253A (en)

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