JPS607552A - Program test device - Google Patents

Abstract

PURPOSE:To know easily and accurately the cause of a fault by designating an address where the fault occurs and its range. CONSTITUTION:The address where a fault occurs is set by an address setting circuit 5, and the upper and lower allowance levels are set by a comparison data range setting circuit 6 for the contents of an address memory. While the value of a program counter 2 is read by a register circuit 7 synchronously with the replacement of the counter 2 of a computer 1. At the same time, the value of a data register 3 which shows the contents of an address set by the circuit 5 is read by a register circuit 8. A comparator 9 compares the value read by the circuit 8 with the value set by the circuit 6. Then the contents of the counter 2 held at the circuit 7 are displayed at a display circuit 10 together with the contents of the register 3 held at the circuit 8 by the output of the comparator 9.

Description

[Detailed description of the invention] The present invention relates to a program testing device.

In programs, various failures often occur due to the occurrence of unexpected information in memory.

Therefore, it is important to know where the abnormal content was written and the cause thereof. Conventionally, a trace function that outputs the execution result every time a program instruction is executed, or a snapshot dump function that outputs the execution result when an instruction at a specific address is executed, etc., were incorporated into the program and used. There was a drawback that it was not possible to know with certainty when the intended data changed. Additionally, changes may be required to the original program.

This invention eliminates such drawbacks and allows you to easily specify the address where the abnormality has occurred and the range of its data.
Moreover, the present invention provides a hardware-based program testing device that can reliably determine the cause of an abnormality.

Embodiments of the present invention will be described in detail with reference to the following two drawings.

The figure is a block diagram showing one embodiment of the present invention. t
, (X) is a microprogrammed computer loaded with the program to be tested.

(2) is the program counter in the computer, (3) is the data register in the computer, (4) is the address register in the computer, and (5) is the address setting for setting the address of the memory in the computer to be referenced. (6) is a comparison data range setting circuit for setting the range of comparison data values, (7) is a register circuit for reading and holding the contents of the program counter, (8) is an address setting circuit (5)
(9) a register circuit that stores the contents of the data register (3) in the computer corresponding to the set address;
α is a comparison circuit that checks whether the contents of the data register (3) are within the range set by the comparison data setting circuit;
is a display circuit that displays the contents of the program counter and data register.

(11a) and (1lb) are registers indicating the allowable upper limit value and allowable lower limit value of the comparison data range.

In such a configuration, first, the address setting circuit (5)
The address where the error occurred is set, and the allowable upper and lower limits of the memory contents at the address are set in the comparison data range setting circuit (6).

On the other hand, in synchronization with the update of the program counter (2) of the computer (1), the program counter (2) is updated from the computer (1).
) is read into the first register circuit (7).

The value of the data register (3) indicating the contents of the address set by the address setting circuit (5) is read into the second register circuit (8). Then, the second register circuit (
8) and the comparison data range setting circuit (
Register (11a) indicating the allowable upper limit value set in 6)
A comparator circuit (9) compares the value and the register (1lb) indicating the allowable lower limit value. If the value read into the second register circuit (8) is larger than the contents of the register (11a) or smaller than the contents of the register (1lb), a control signal from the comparator circuit (9) is sent. Then, the contents of the program counter (2) held in the first register circuit (7) and the contents of the data register (3) held in the second register circuit (8) are displayed through the display circuit 0. do.

In addition, in the microprogrammed computer (1), the shear address register (4) is set by the microprogram.
) is always stored in the data register (3).

As described above, according to the present invention, when the value of the memory in the specified computer becomes an abnormal value outside the predetermined range, it is possible to easily know which program was used to write the data, and the program can be tested. It is effective when

[Brief explanation of the drawing]

The figure is a block diagram showing an embodiment of the program test device according to the present invention. In the figure, (1) is a computer, (2)
is the program counter in the computer, (3) is the data register in the computer, (4) is the address register in the computer, (5) is the address setting circuit, (6) is the comparison data range setting circuit, and (7) is the data register in the computer. 1 register circuit, (8) is the second register circuit.
(9) is a comparison circuit, (9) is a display circuit, (9) is a display circuit, (
11a) and (11b) are registers. Agent Masuo Oiwa

Claims (1)

[Scope of Claims] An address setting circuit for setting an address to retrieve contents in the memory of a computer, and a system for reading the contents of the memory in the computer and the program counter in the computer set by the address setting circuit. . means for storing the content, a comparison data range setting circuit for setting the allowable upper limit value and allowable lower limit value for checking the read memory content, and a comparison data range setting circuit for setting the allowable upper limit value and allowable lower limit value for checking the read memory content, and the allowable upper limit value set by the above setting circuit for checking the read memory content. 1. A program test device comprising: a comparison circuit for comparing whether or not a value and a range of allowable lower limit values are satisfied.