JPS63201737A - Method and device for supporting development of computer program - Google Patents

Abstract

PURPOSE:To easily detect execution of an abnormal instruction whose reproducibility is low, by detecting an execution of a write instruction to a specific address of a memory from various signals outputted from a computer, displaying and holding its instruction executing address, detecting an execution of a mask instruction immediately before executing a write instruction and inhibiting the displaying and holding. CONSTITUTION:Setting of a flip-flop 17 by a memory write address comparing and deciding circuit 9 is inhibited by cutting off a mask circuit 23 by an output of the mask instruction detecting circuit 14. Also, only when there is no output of the mask detecting circuit 14, the flip-flop 17 is set by the output of the memory write address comparing and detecting circuit 9, an instruction executing address which an instruction executing address display circuit 5 is executing at present is displayed and held, and the display is updated successively. In such a way, by only changing a set address of an address setting switch 15, an execution of an abnormal write instruction to an arbitrary address of a memory is detected and can be informed to an operator.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is intended to support software development (computer program development) for computers. The present invention relates to a computer program development support method and apparatus for detecting an abnormal write instruction to a specific address of a memory from various output signals.

[Conventional technology]

Conventional computer program development support devices monitor various signals output from a computer running a computer program, and stop the computer when the number of occurrences of a break condition reaches a predetermined number (one or more times). I was supposed to do debugging work.

[Problem that the invention seeks to solve]

Conventional computer program development support devices such as those described above can be used in environments where it is difficult to stop the computer for debugging when a break condition occurs, such as in control systems used in actual operations, or during long-term use. It cannot be used as a countermeasure for factors for which it is difficult to reliably reproduce the problem.

In addition, the same break condition may occur even when a normal instruction is executed, making it difficult to distinguish it from a break condition occurring when an abnormal instruction is executed, making it difficult to find the location of the bug using the method of specifying the number of times. be.

An object of the present invention is to provide a computer program development support method and apparatus capable of reliably distinguishing and detecting abnormal instructions present in a computer program from normal instructions without stopping computer operation, and informing the operator of the detected abnormal instructions. It is to provide.

[Means for solving problems]

The computer program development support method of the first invention includes:
A mask command is inserted immediately before a normal write command to a specific memory address in a computer program, and the memory is identified from various signals output from the computer while the computer program is being executed by the computer. Detects the execution of a write command to an address, holds the command execution address of the write command, and detects the execution of a mask command immediately before the execution of the write command to a specific address of the memory, and detects the execution of the write command to a specific address of the memory. This is a method of detecting from a signal and prohibiting holding of the instruction execution address of the write instruction.

The computer program development support device of the second invention includes:
A computer program development support device for detecting an abnormal write instruction to a specific address of a memory in a computer program in which a mask instruction is inserted immediately before a normal write instruction to a specific address of the memory, the computer program development support device comprising: an address setting switch for setting an address; and a memory write for detecting various signals output from a computer executing the computer program and execution of a write command from the setting address set by the address setting switch to the setting address of the memory. An address comparison/judgment circuit, a flip-flop that is set in response to the output of the memory write address comparison/judgment circuit, and various signals outputted from the computer in response to the reset output of this flip-flop determine the current state of the computer. an instruction execution address display circuit that updates and displays the execution address of the instruction being executed and maintains the display of the instruction execution address in response to the set output of the flip-flop; A mask instruction detection circuit for detecting execution of a mask instruction, interposed between the memory write address comparison and determination circuit and the flip-flop, and generating an output of the mask instruction detection circuit in response to an output of the mask instruction detection circuit. and a mask circuit that cuts off the output of the memory write address comparison/judgment circuit immediately after.

[Effect]

According to the configuration of the first invention, a mask instruction is inserted immediately before a normal write instruction to a specific address of memory in a computer program, and while the computer program is being executed, the mask instruction is inserted into the computer program. The execution of a write command to a specific address is detected from various signals output from the computer, the command execution address of the write command is displayed and held, and the execution of a mask command immediately before the execution of the write command is detected. In order to prohibit the above display,
When a normal write instruction to a specific memory address exists in a computer program, a mask instruction also exists immediately before it, and the instruction execution address is displayed when the normal write instruction is executed by executing the mask instruction. Retention is prohibited. On the other hand, when there is an abnormal write instruction to a specific memory address in a computer program, no mask instruction is inserted immediately before it, so when the abnormal write instruction is executed, the instruction The display of the execution address is maintained. Therefore, it is possible to detect an abnormal write command to a specific memory address existing in a computer program without stopping the operation of the computer, distinguishing it from a normal write command, and to notify the operator of the abnormal write command. Furthermore, since the command execution address of the abnormal write command is displayed and retained, the operator can know the abnormal write command without constantly monitoring it, and the burden is placed on the operator to detect abnormal command execution with low reproducibility. You can do it without spending money.

According to the configuration of the second invention, an address setting switch is provided, and the setting address set by the address setting switch is sent to the memory write address comparison/judgment circuit, so that all that is required is to change the setting address of the address setting switch. It is possible to detect the execution of an abnormal write command to any address in memory and notify the operator.

〔Example〕

An embodiment of the invention will be described based on FIGS. 1 to 3. This computer program development support method inserts a mask command immediately before a normal write command to a specific memory address in a computer program, and when the computer program is being executed by the computer 1, a mask command is inserted into the computer program. Detects the execution of a write command to a specific address of the memory from various output signals (address signals, control signals), holds the command execution address of the write command, and writes to the specific address of the memory. This method detects execution of a mask instruction immediately before execution of the instruction from various signals (address signal, control signal) output from the computer 1 and prohibits holding of the instruction execution address of the write instruction.

According to this computer program development support method, a mask command is inserted immediately before a normal write command to a specific memory address in a computer program, and while the computer program is being executed by the computer 1, the mask command is inserted into the memory. Various signals (address signals) output from the computer 1 indicate the execution of a write command to a specific address.

In order to display and hold the command execution address of the write command by detecting it from the control signal), and to detect the execution of the mask command immediately before the execution of the write command and prohibit the display holding, the memory is stored in the computer program. When a normal write command to a specific address exists, a mask command also exists immediately before it, and execution of the mask command prohibits display and retention of the instruction execution address when a normal write command is executed. .

On the other hand, when there is an abnormal write instruction to a specific address in memory in a computer program, no mask instruction is inserted immediately before it, so when the abnormal write instruction is executed, the instruction cannot be executed. The address is kept displayed. Therefore, without stopping the operation of the computer 1, an abnormal write command to a specific memory address existing in a computer program can be detected as distinguished from a normal write command, and the operator can be notified of the abnormal write command. Furthermore, since the command execution address of the abnormal write command is displayed and retained, the operator can know the abnormal write command without constantly monitoring it, and the operator can also detect the execution of abnormal commands with low reproducibility. It can be done without any burden.

Next, a computer program development support device used to implement this computer program development support method will be explained based on FIG.

This computer program development support device detects an abnormal write instruction to a specific memory address in a computer program in which a mask instruction is inserted immediately before a normal write instruction to a specific memory address. The apparatus comprises: an address setting switch 15 for setting the address of the memory; and a computer (for executing the computer program).
Memory write address comparison for detecting execution of a write command from the set address set by the address setting switch 15 to the set address of the memory with various signals (address signal, data signal, control signal) output from the CPU) 1 From the side leg circuit 9, the flip-flop 17 that is set in response to the output of the memory write address comparison/determination circuit 9, and the various signals output from the computer 1 in response to the reset output of the flip-flop 17. an instruction execution address display circuit 5 that updates and displays an instruction execution address currently being executed by the computer 1 and maintains a display of the instruction execution address in response to a set output of the flip-flop 17; a mask instruction detection circuit 14 that detects the execution of the mask instruction from various signals output from the mask instruction detection circuit 14, which is interposed between the memory write address comparison judgment circuit 9 and the flip-flop 17, and and a mask circuit 23 that cuts off the output of the memory write address comparison/judgment circuit 9 immediately after the output of the mask command detection circuit 14 is generated in response to the output.

In addition to the above-mentioned function for detecting abnormal write commands to memory, this computer program development support device also has a function for detecting abnormal successive commands to memory, abnormal input/output commands to input/output devices, etc. ing.

In other words, this computer program development support device uses an address bus 2. drawn from the computer 1. Data bus 3. An instruction execution address display circuit 5. Execution command box display circuit 6. Instruction execution address comparison and determination circuit 7゜Memory read address comparison and determination circuit 8. Memory write address comparison judgment circuit 9. Memory read/write address comparison/judgment circuit 10. I10 Read address comparison judgment circuit 1). 1) 0 write address comparison judgment circuit 12. l10U-D write address comparison judgment circuit 13. A mask command detection circuit 14 is connected.

Further, the address line drawn out from the address setting switch 15 and each selection terminal of the abnormality detection function selection switch 16 are connected to the instruction execution address comparison and determination circuit 7. Memory read address comparison judgment circuit 8. Memory write address comparison judgment circuit 9. Memory read/write address comparison judgment circuit 1
0.1) 0IJ-Address Comparison Judgment Circuit 1). I10
Write address comparison/judgment circuit 12. The I10 read/write address comparison/judgment circuit 13 is connected to the I10 read/write address comparison/judgment circuit 13, respectively.

Further, the common terminal of the abnormality detection function selection switch 16 and the output terminal of the mask command detection circuit 23 are connected to the mask circuit 23, and the output terminal of the mask circuit 23 is connected to the flip-flop 1.
7 is connected to the set input terminal S of the reset switch 19.
The output of the NOT circuit 18 that inverts the state of is connected to the reset input terminal R of the flip-flop 17, and the output terminal Q of the flip-flop 17 is connected to the control input terminals of the instruction execution address display circuit 5 and the execution instruction content display circuit 6. has been done.

The instruction execution address display circuit 5 includes a flip-flop 17
The instruction execution address of the instruction currently being executed by the computer 1 is displayed while being updated sequentially when the computer 1 is reset, and the display of the instruction execution address of the instruction currently being executed by the computer 1 is held when the flip-flop 17 is set.

The executed instruction content display circuit 6 sequentially updates and displays the content of the instruction currently being executed by the computer 1 when the flip-flop 17 is reset, and displays the content of the currently executed instruction when the flip-flop 17 is set. Hold.

The instruction execution address comparison and determination circuit 7 generates an output when the instruction execution address of the instruction executed by the computer l matches the address set by the address setting switch 15.

The memory read address comparison/determination circuit 8 generates an output when the memory read address in the successive command executed by the computer 1 matches the address set by the address setting switch 15.

The memory write address comparison/determination circuit 9 generates an output when the memory write address in the write command executed by the computer 1 matches the set address.

The memory read/write address comparison/determination circuit 10 generates an output when either the memory read address in the successive command or the memory ride address in the write command executed by the computer 1 matches a set address.

The I10 read address comparison/judgment circuit 1) generates an output when the I10IJ- address in the input command executed by the computer 1 matches the set address.

The I10 write address comparison and determination circuit 12 generates an output when the I10 write address in the output instruction executed by the computer 1 matches the set address.

The I10 read/write address comparison/judgment circuit 13 generates an output when either the I10 read address in the input command or the I10 write address in the output command executed by the computer 1 matches a set address.

The mask command detection circuit 14 detects from the address signal, data signal, and control signal output from the computer 1 that the computer 1 has executed a mask command. In addition,
Execution of a mask instruction by the computer 1 means outputting certain data to an output port at a specific address dedicated to the mask instruction detection circuit 14. The mask instruction detection circuit 14 detects only when the output port of the specific address is selected, and the data to be output does not have to have a specific content, thereby allowing the computer 1 to execute the mask instruction. However, the execution of the mask command by the computer 1 may be detected by detecting that specific data dedicated to masking is output to the output port at the above-mentioned specific address.

The mask circuit 23 includes a flip-flop 20 to which the output of the mask command detection circuit 14 is input to the set input terminal S and, for example, the output of the memory write address comparison/judgment circuit 9 to the reset input terminal R;
0 inverted output terminal From an on-delay type (rise delay type) delay circuit 21 that delays this output, and an AND circuit 22 that takes the logical product of the output of the memory write address comparison/judgment circuit 9 and the output of the delay circuit 21, for example. The output terminal of the AND circuit 22 is connected to the set input terminal S of the flip-flop 17.

This computer program development support device runs a computer program in which a mask command is inserted in advance immediately before a write command to the memory in a state in which the abnormality detection function selection switch 16 is switched to, for example, the memory write address comparison judgment circuit 9. When executed, the memory write address comparison judgment circuit 9. Mask command detection circuit 1
4. Mask circuit 23. Flip-flop 17 operates as follows. That is, the memory write address comparison and determination circuit 9 constantly determines whether a write command to the set address of the memory has been executed based on the address signal and control signal output from the computer 1 and the address set by the address setting switch 15. Furthermore, the mask command detection circuit 14 constantly determines whether a mask command has been executed based on the address signal and control signal output from the computer 1. First, when the computer 1 executes a mask instruction, the mask instruction detection circuit 14 detects from the address signal and control signal output from the computer 1 that the computer 1 has executed the mask instruction, and generates an output. When an output is generated from the mask command detection circuit 14, the mask circuit 23 enters a cut-off state.

Thereafter, when the computer 1 executes a write command, the memory write address comparison/determination circuit 9 generates an output. However, the mask circuit 23 is in a cut-off state, and the flip-flop 17 is not set. Therefore, the instruction execution address display circuit 5 sequentially updates and displays the instruction execution addresses of the instructions being executed by the computer 1, and the execution instruction content display circuit 6 similarly updates and displays the contents of the instructions. That is, since the mask command is placed before the write command for the set address of the memory, even if the write command is executed, the display of the command execution address display circuit 5 and the execution command content display circuit 6 is not maintained.

On the other hand, when the computer 1 executes a computer program in which a mask instruction is not inserted immediately before a write instruction to the memory, the memory write address comparison judgment circuit 9
．． Mask command detection circuit 14° mask circuit 23. Flip-flop 17 operates as follows. That is, the memory write address comparison and determination circuit 9 constantly determines whether a write command to the set address of the memory has been executed based on the address signal and control signal output from the computer 1 and the address set by the address setting switch 15. , and the mask command detection circuit 14 is connected to the computer 1.
It is determined whether the mask command has been executed based on the address signal and control signal output from the . In this case, since the computer 1 does not execute the mask command, the mask command detection circuit 14 does not generate an output, and the mask circuit 2
3 is not in the cutoff state.

Therefore, when computer 1 executes a write command,
Memory write address comparison/determination port B9 generates an output. At this time, since the mask circuit 23 is not in the cut-off state, the flip-flop 17 is set. Therefore, the instruction execution address display circuit 5
stops sequentially updating the instruction execution address of the instruction being executed and maintains the displayed state of the instruction execution address of the write instruction, and the executed instruction content display circuit 6 similarly stops updating the instruction content and displays the Retains the display of the command contents at the time. That is, since there is no mask command for the set address of the scale, the display of the command execution address display circuit 5 and the execution command content display circuit 6 is maintained when the write command is executed.

If the write command described above is a normal command, a mask command is inserted immediately before it, so the computer 1 executes the mask command, and the mask command detection circuit 14 detects the execution of the mask command by the computer 1 (specific signal output to the output port), and prohibits the setting of the flip-flop 17 when executing a write command, prohibits the instruction execution address display circuit 5 and the execution instruction content display circuit 6 from holding the display, and restarts the resetting operation. Let it continue.

On the other hand, if the above write command is an abnormal command (bug),
The computer 1 does not execute the mask instruction, the setting of the flip-flop 17 is not prohibited, and the flip-flop 17 is set by executing the write instruction, and the display of the instruction execution address display circuit 5 and the execution instruction content display circuit 6 is maintained. and will remain until the flip-flop 17 is reset by the reset switch 19.

Next, the operation of the mask circuit 23 will be explained with reference to FIGS. 2 and 3. FIG. 2 is a time chart of each part when there is a mask command before a write command, and FIG. 3 is a time chart of each part when there is no mask command before a write command. 2 and 3, (A) shows the output of the mask instruction detection circuit 14, (B) shows the Q output of the flip-flop 20, (C) shows the output of the delay circuit 21, and (D
) shows the output of the AND circuit 22, (E) shows the output of the memory write address comparison/judgment circuit 9, and (F) shows the output of the flip-flop 17, respectively.

First, the operation when there is a mask command will be explained with reference to FIG. In the initial state, the output of the mask command detection circuit 14 is at the L level as shown in FIG. 2(A), the n output of the flip-flop 20 is at the H level as shown in FIG. 2(B), and the output of the delay circuit 21 is is at the H level as shown in FIG. 2(C), the output of the AND circuit 22 is at the L level as shown in FIG. 2(D), and the output of the memory write address comparison/judgment circuit 9 is at the H level as shown in FIG.
), the Q output of the flip-flop 17 is at the L level, as shown in FIG. 2(F).

In this state, the instruction execution address display circuit 5 and the execution instruction content display circuit 6 are updating their displays.

After this, the mask command is executed and the mask command detection circuit 1
When the output of 4 becomes H level as shown in FIG. 2(A), the d output of flip-flop 20 immediately becomes L level as shown in FIG. 2(B), and furthermore, the output of delay circuit 21 also becomes H level as shown in FIG. It immediately goes to L level as shown in (C). At this time, since the output of the memory write address comparison/determination circuit 9 is at L level as shown in FIG. 2(E), the AND circuit 22
The output of the flip-flop 17 is maintained at the L level as shown in FIG. 2(D), and therefore the output Q of the flip-flop 17 is also at the L level as shown in FIG. 2(F). The circuit 6 maintains the display update state.

Thereafter, when a write command to a predetermined set address of the memory is executed, the memory write address comparison and determination circuit 9
The output becomes H level as shown in FIG. 2(E). As a result, the flip-flop 20 is reset and the Q output returns to the H level as shown in FIG.
After D, the output of the delay circuit 21 becomes H as shown in Fig. 2(C).
Return to level. At this time, even if the output of the memory write address comparison/judgment circuit 9 becomes H level, the time TI
Since the output of the medium delay circuit 21 maintains the L level,
The output of the AND circuit 22 remains at the L level as shown in FIG. 2(D), so the flip-flop 17 is not set and its Q output also remains at the L level as shown in FIG. 2(F). , the instruction execution address display circuit 5 and the execution instruction content display circuit 6 maintain the display update state.

When the output of the delay circuit 21 returns to H level, the initial state is returned.

As described above, if a mask instruction is inserted before a write instruction, even if the write instruction is executed, the flip-flop 17 is not set, and the instruction execution address display circuit 5 and execution instruction content display circuit 6 will maintain the display update state. In order to perform the above operation, it is necessary to set the delay time TD of the delay circuit 21 to be longer than the time T1 during which the output of the memory write address comparison and determination circuit 9 is at the H level.

Next, the operation when there is no mask command will be explained with reference to FIG. In the initial state, the mask command detection circuit 14
The output of the flip-flop 20 is at the L level as shown in FIG. 3 (A>), the six outputs of the flip-flop 20 are at the H level as shown in FIG. 3(B), and the output of the delay circuit 21 is at the H level as shown in FIG. 3(C). level, the output of the AND circuit 22 is at L level as shown in FIG. 3(D),
The output of the memory write address comparison/judgment circuit 9 is shown in FIG.
The Q output of the flip-flop 17 is at the L level as shown in FIG. 3(F).

In this state, the instruction execution address display circuit 5 and the execution instruction content display circuit 6 are updating their displays.

If no mask command is inserted, the output of the mask command detection circuit 14 remains at the L level as shown in FIG. 3(A), and the σ output of the flip-flop 20 remains at the L level as shown in FIG. 3(B). It maintains the H level state, and the output of the delay circuit 21 also maintains the H level state as shown in FIG. 3(C).

When a write command to a predetermined set address of the memory is executed, the output of the memory write address comparison/determination circuit 9 becomes H level as shown in FIG. 3(E). As a result, the output of the AND circuit 22 becomes H level as shown in FIG. 3(D), and therefore the flip-flop 17 is set.
The Q output becomes H level as shown in FIG. 3(F), and the instruction execution address display circuit 5 and execution instruction content display circuit 6 change to the display holding state. This state continues until the flip-flop 17 is reset by the reset switch 19.

Note that even when the abnormality detection function selection switch 16 is switched to another position, the same operation as described above will be performed, except that the object of abnormality detection is different.

Here, abnormal write commands and normal write commands will be explained a little more. Consider a case where a computer program contains the following series of abnormal instructions.

100HLD A, 0FFH102□
LD HL, 1000H105TI LD
(HL), A The meaning of the above command group is to write data OFF□ to the A register, write data 1000H to the HL register, and write the A register to the memory address (address 1000H) indicated by the contents of the HL register. Writing the contents (OFFH) means writing data 0FFH to address 1000H of the memory. If such a series of instructions exists in a computer program, when the address setting switch 15 is set to 1000H, the computer 1
When the instruction execution address 105H is executed, the instruction execution address display circuit 5 displays and holds "105H".

Next, let us consider the case where the following sequence of normal instructions exists in a computer program.

200HOUT (01,), A 202HLD A, OFF□204,
T LD HL, 2000□20? H
LD (HL), A The meaning of the above command group is to output the contents of the A register to the 01H output port (mask command), write data 0FFH to the A register, write data 2000H to the HL register, Memory address (2) indicated by the contents of the H register.
This means writing the contents of the A register (OFFH) to address 000H), that is, outputting data 0FFH to the output port numbered 01H, and then writing data 0FFH to address 2000□ of the memory. If such a series of instructions exists in a computer program, even if the computer 1 executes the instruction at address 207H when the address setting switch 15 is set to 2000H, the instruction execution address display circuit 5 will not hold the display. Not performed.

The computer program development support device of this embodiment is
The memory write address comparison/judgment circuit 9 detects the execution of a write command to the set address of the memory based on various signals output from the computer 1 and the set address of the address setting switch 15, and the mask command detection circuit 1
4 detects the execution of a mask instruction from various signals output from the computer 1, and blocks the mask circuit 23 with the output of the mask instruction detection circuit 14, thereby causing the memory write address comparison and determination circuit 9 to set the flip-flop 17. The flip-flop 17 is set by the output of the memory write address comparison/judgment circuit 9 only when there is no output from the mask detection circuit 14, and the current instruction execution address display circuit 5 is set in response to the set output of the flip-flop 17. Since the execution address of the instruction being executed is displayed and held, and the instruction execution address display holding circuit 5 sequentially updates the display in response to the reset output of the flip-flop 17, simply changing the setting address of the address setting switch 15 is enough. Execution of an abnormal write command to an arbitrary address in memory can be detected and notified to the operator.

〔Effect of the invention〕

According to the computer program development support method of the first invention, a mask instruction is inserted immediately before a normal write instruction to a specific address of memory in the computer program,
While the computer program is being executed by the computer, the execution of a write command to a specific address of the memory is detected from various signals output from the computer, and the command execution address of the write command is displayed and held; In order to detect the execution of a mask command immediately before the execution of the above write command and prohibit the above display retention, if there is a normal write command to a specific memory address in the computer program, the mask command is also executed immediately before it. Execution of a mask instruction prohibits display and retention of the instruction execution address when a normal write instruction is executed. On the other hand, when there is an abnormal write instruction to a specific memory address in a computer program, no mask instruction is inserted immediately before it, so when the abnormal write instruction is executed, the instruction The display of the execution address is maintained. Therefore, it is possible to detect an abnormal write command to a specific memory address existing in a computer program without stopping the operation of the computer, distinguishing it from a normal write command, and to notify the operator of the abnormal write command.

Furthermore, since the command execution address of the abnormal write command is displayed and retained, the operator can know the abnormal write command without constantly monitoring it, and the burden is placed on the operator to detect abnormal command execution with low reproducibility. You can do it without spending money.

According to the computer program development support device of the second invention, since the address setting switch is provided and the setting address set by the address setting switch is sent to the memory write address comparison judgment circuit, the setting address of the address setting switch is By simply changing , it is possible to detect abnormal execution of a write command to any address in memory and notify the operator.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIGS. 2 and 3 are time charts of each part of FIG. 1. DESCRIPTION OF SYMBOLS 1... Computer, 5... Instruction execution address display circuit, 9... Memory write address comparison judgment circuit, 1
4...Mask command detection circuit, 15...Address setting switch, 17...Flip-flop, 23...Mask circuit second factor and third factor

Claims (2)

[Claims] (1) A mask command is inserted immediately before a normal write command to a specific memory address in a computer program, and while the computer program is being executed by the computer, various signals output from the computer Detecting the execution of a write instruction to a specific address in memory, holding the instruction execution address of the write instruction, and outputting from the computer the execution of the mask instruction immediately before the execution of the write instruction to the specific address in the memory. A computer program development support method that detects from various signals sent to the write command and prohibits holding of an instruction execution address of the write command. (2) A computer program development support device that detects an abnormal write instruction to a specific memory address in a computer program in which a mask instruction is inserted immediately before a normal write instruction to a specific memory address, an address setting switch for setting the address of the memory; various signals output from a computer executing the computer program; and detection of execution of a write command from the setting address set by the address setting switch to the setting address of the memory; A memory write address comparison/judgment circuit that performs the memory write address comparison/judgment circuit, a flip-flop that is set in response to the output of the memory write address comparison/judgment circuit, and various signals output from the computer in response to the reset output of this flip-flop. an instruction execution address display circuit that updates and displays an instruction execution address currently being executed by the computer and maintains a display of the instruction execution address in response to the set output of the flip-flop; and various outputs from the computer. a mask instruction detection circuit that detects execution of the mask instruction from a signal; and a mask instruction detection circuit that is interposed between the memory write address comparison and determination circuit and the flip-flop and responds to the output of the mask instruction detection circuit. and a mask circuit that cuts off the output of the memory write address comparison/determination circuit immediately after the output of the memory write address comparison/judgment circuit is generated.