JPS61109152A - Malfunction detector - Google Patents

Abstract

PURPOSE:To facilitate an analysis of a fault due to a program mistake by comparing a branch destination address with the program areas of a monitor part and an executing module respectively. CONSTITUTION:The addresses showing the program areas of a monitor part are set to address registers 20 and 21, and an FF26 is set by the enable signal given from an instruction decoder 11. Thus a comparator 24 is set under an enable state and a malfunction detecting state stands by. Then the addresses showing the areas of an executing module are set to address registers 22 and 23. The comparator 24 compares a branch destination address 31 with addresses stored in the registers 20-23 respectively every time a branch instruction 32 is delivered from the decoder 11 in a microprogram controller 1. Thus a malfunction is detected with the controller 1.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a malfunction detection device, and more particularly to a malfunction detection device for a microprogram control device in a data processing device.

Conventionally, this type of microprogram control device has been composed of a plurality of program modules as shown in FIG. Each execution module is configured to execute a program based on a command from the monitor section, and return to the monitor section again when the execution operation is completed. In addition, a subroutine prepared by the monitor section may be called as necessary. In this way, each execution module controls the program only with the monitor section, and never goes to any execution module other than the monitor section.

However, in program development, etc., branching to other execution modules often occurs due to a program error or the like. In this case, the problem is that an error does not occur in an execution module with a programming error, but an error occurs in an execution module that was originally branched by mistake, and an enormous amount of time is required to analyze failures caused by this programming error. There are downsides to being spent.

The present invention was made in order to eliminate the drawbacks of the conventional upper part, and its purpose is to provide a malfunction detection device that can easily and reliably detect failures caused by program errors. be.

Composition of the Invention The malfunction detection device according to the present invention is aimed at a malfunction detection device in a microprogram control device composed of a plurality of program modules, and is characterized by the ability to detect a program area of a monitor section in a program module. The first one that stores the upper and lower limit addresses of the monitor section.
a storage means, a second storage means for storing execution module upper and lower limit addresses indicating a program area of an execution module to be executed in a program module, and a first and second storage means for storing a branch destination address when a branch instruction is issued. has a detection means for detecting whether or not the detection means exists within the upper and lower limit address ranges of The purpose is to enable the detection of malfunctions in the microprogram control device.

Another malfunction detection device according to the present invention includes, in addition to the above-described configuration, a holding means for holding the value of the program counter when a branch instruction is issued, and identifies an execution program module in which an error has occurred based on the contents held in this holding means. It is characterized by being possible.

K Yutakaj Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 2 is a block diagram of an embodiment of the invention.

Reference numeral 1 denotes a microprogram control device, and in the figure, only the functional parts necessary for the present invention are extracted and shown for the sake of simplicity. 10 is a program counter, 11 is an instruction decoder, 30 is a data bus line, and 31 is an address bus line.

2 is a malfunction detection device according to the present invention, 20 is a monitor unit upper limit address register, and 21 is a monitor lower limit address register, and these registers 20 and 21 determine the program area range of the monitor unit. 2'2 is an execution module upper limit address register, 23 is an execution module lower limit address register, and both registers 22.2
3, the execution module area range to be executed is determined. A comparison circuit 24 compares the stored outputs of the four address registers 20 to 23 with the address on the address bus 31. 25 is a program counter register, and the program counter 10
It holds the value of . Reference numeral 26 denotes an FF (flip-flop), which controls the enable/disable state of the comparison circuit 24.

32 is a branch command signal, 33 is an address register 20
A signal 34 determines the timing of setting the corresponding addresses to FF26.

When detecting a malfunction with such a configuration, first,
The monitor section program stores the monitor section upper limit and lower limit addresses indicating the monitor section program area in the address register 2, respectively.
At the same time, the enable signal 34 is issued from the instruction decoder 11 and the FF 26 is set. Therefore, the comparator circuit 24 is enabled and the malfunction detection state is put on standby. Next, before passing control to the execution module, the monitor section sets the execution module upper limit and lower limit addresses indicating the area of the execution module in the address registers 22 and 23, respectively. The area of each execution module may be located at a specific address within the monitor section or at a predetermined address for each execution module. When each of the above setting operations is completed, the monitor section transfers control to the execution module.

The comparison circuit 24 compares the branch destination address (31) with the storage address of each address register 20-23 every time a branch instruction 32 is issued from the instruction decoder 11 in the microprogram control device 1. Here, if it is detected from the comparison result of this comparison circuit 24 that this branch destination address does not exist in any range within the program area or execution module area of the monitor unit, it is determined that the branch destination is incorrect. This detection output is sent to the microprogram controller. Based on this detection output, for example, a CPU (central processing unit) (not shown) is interrupted to display a malfunction of the microprogram control device on a display device or the like.

On the other hand, the detection output from the comparison circuit 24 is also sent to the program counter register 25, and the program counter register 25 normally reads the value of the program counter 10 of the microprogram control device 1 every time the branch instruction signal 32 is issued. Since it is designed to store
At the timing of generation of this detection output, the current value of the program counter 10 is set in this register 25 and held thereafter. Since this set value is sent to the microprogram control device 1,
If this value is displayed on a display device or the like, it becomes easy to identify the execution module that caused the malfunction.

If malfunction detection is not required, the instruction decoder 11
If a reset signal for resetting the FF 26 is generated by the above, the comparator circuit 24 will be in a disabled state and no malfunction detection operation will be performed.

Now, if you always check the branch destination area, before passing control from the monitor section to the execution module, you will need to set the execution module upper and lower limit addresses that indicate the area of the execution program section in the address registers respectively. Therefore, the so-called overhead time of the program increases. Therefore, according to the present invention, the comparison circuit 24 is deactivated during normal times when no malfunction detection operation is required, thereby preventing an increase in overhead time.

In the above embodiment, the malfunction detection device 2 is provided separately from the microprogram control device 1.

These may also be provided integrally.

[1] According to the present invention, since the branch destination address and the program area of the monitor section and the execution module are compared, it is possible to easily and reliably analyze failures caused by programming mistakes. By retaining the value of the program counter at the time of occurrence, it becomes possible to identify the execution module in which the program error occurred. Furthermore, since activation and deactivation of malfunction detection are controlled, malfunction detection can be performed only when necessary, and an increase in program overhead time can be prevented.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of microprogram mapping, and FIG. 2 is a block diagram of an embodiment of the present invention. Explanation of symbols of main parts 1...Microprogram control device 2...
... Malfunction detection device 10 ... Program counter 11 ... Instruction decoders 20 to 22 ... Address register 24 ...
... Comparison circuit 25 ... Program counter register 26 ...
...FF

Claims (2)

[Claims] (1) A malfunction detection device for a microprogram control device constituted by a plurality of program modules, the device comprising: a first storage means for storing upper and lower limit addresses of a monitor section indicating a program area of a monitor section in the program module; , a second storage means for storing execution module upper and lower limit addresses indicating a program area of an execution module to be executed in the program module;
detection means for detecting whether a branch destination address at the time of issuing a branch instruction exists within the upper and lower limit address ranges of the first and second storage means, and control for controlling the activation and deactivation of the detection operation of this detection means. What is claimed is: 1. A malfunction detection device comprising means for detecting a malfunction of a microprogram control device using a detection output when said detection means is activated. (2) A malfunction detection device for a microprogram control device constituted by a plurality of program modules, comprising a first storage means for storing upper and lower limit addresses of a monitor section indicating a program area of a monitor section in the program module; , a second storage means for storing execution module upper and lower limit addresses indicating a program area of an execution module to be executed in the program module;
detection means for detecting whether a branch destination address at the time of issuing a branch instruction exists within the upper and lower limit address ranges of the first and second storage means, and control for controlling the activation and deactivation of the detection operation of this detection means. a holding means for holding the value of the program counter when the branch instruction is issued; and a detection output when the detecting means is activated and a holding output of the holding means to cause malfunctions and program errors in the microprogram control device. A malfunction detection device characterized in that a module can be detected freely.