JPH04182839A - Debugging system for microprogram - Google Patents

Abstract

PURPOSE:To remove the restriction of the number of circuits on an address to be debugged by reading a flag out of a corresponding address of a flag storage memory and deciding that an address of a main memory which is accessed when the flag is detected is the address to be debugged. CONSTITUTION:A flag control switch 4 outputs a debugging trigger address 12 onto an address bus 6 and also sets a flag on the flag storage memory 3 with a flag setting signal 9 and then the switch 4 releases a microprocessor 1 from being held. The processor 1 reads an instruction code out of the main memory 2 again and performs a normal process. The processor 1 outputs the address of the memory 2 to the bus 6 and the memory 2 is accessed. At the same time, the flag is read out of the address of the memory 3 corresponding to the address of the memory 2 accessed through the bus 6 as a flag state signal 10, which is checked by a flag detecting circuit 5. When the memory 2 is accessed to output the address 12 to the bus 6, the processor 1 is informed of that from the circuit 5 with a debugging information signal 11 and a debugging process starts.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a debugging method for a microprogram of an information processing device.

[Conventional technology]

Traditionally, the debugging method for this type of microprogram is
The main memory address to be debugged is set in the auxiliary memory circuit in advance, and the main memory address to be debugged set in the auxiliary memory circuit is compared with the main memory address accessed by the microprocessor, and the comparison circuit determines whether the two match. When detected, a match detection signal is reported to the microprocessor, and debug processing is executed from that address.

[Problem to be solved by the invention]

The conventional microprogram debugging method described above requires an auxiliary memory circuit that stores in advance the main memory address that you want to debug. There is a problem in that the number of addresses is limited by the number of auxiliary memory circuits provided in advance.

An object of the present invention is to provide a microprogram debugging method that can increase the number of main memory addresses that can be debugged.

[Means to solve the problem]

A microprogram debugging method of the present invention is a microprogram debugging method having a microprocessor and a main memory storing a microprogram and data generated by execution of the microprogram, which includes: (A) each of the main memories; has a flag storage address in one-to-one correspondence with the address of , and when specifying the address of the main memory at which debugging processing is to be executed, the flag is stored at the flag storage address corresponding to the address of the main memory. , a flag storage memory from which the flag is removed from the flag storage address when execution of debug processing is not instructed; (B) flag storage/removal means for storing and removing the flag; (C) the microprocessor At the same time as accessing the memory address, the flag is read and checked from the flag storage memory address corresponding to the main memory address, and when the flag is stored, the microprocessor is caused to execute the debugging process. It has a flag detection means.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a diagram showing a memory map of the microprogram debugging method of FIG. 1.

The microprogram debugging method shown in FIG. When specifying an address in main memory 2 that has a one-to-one correspondence and where you want to execute debugging,
The flag storage memory 3 stores a flag at an address corresponding to that address, stores (sets) a flag at any address in the flag storage memory 3, or flags set at any address in the flag storage memory 3. remove (reset)
flag control switch (flag storage/removal means) 4,
It consists of a flag detection circuit 5 that checks the flag read out from the flag storage memory 3 and notifies the microprocessor 1 if the flag is set.

Next, the operation will be explained.

In FIG. 1, a microprocessor 1 outputs a memory address to an address bus 6, and a data bus 7 from a main memory 2.
Read the instruction code via.

Then, the read instruction code is executed, and data is read from and written to the main memory 2 by executing the instruction code.

It is assumed that the microprocessor 1 is reading an instruction code from the main memory 2 and executing normal processing, and the flag storage memory 3 is in a state where flags are not stored at all addresses (reset). .

First, the flag control switch 4 activates the hold request signal 8 to place the microprocessor 1 in a hold state. Further, the flag control switch 4 outputs the debug trigger address 12, which is the memory address at which debug processing is to be executed, onto the address bus 6, and at the same time, a flag is set in the flag storage memory 3 by the flag setting signal 9. If there are multiple memory addresses at which debugging is desired, the operation of the flag control switch 4 as described above is repeated. After setting the flag in the flag storage memory 3, the hold request signal 8 is made inactive by the flag control switch 4, and the microprocessor 1
release the hold state.

The microprocessor reads the instruction code from the main memory 2 again and executes normal processing. In the flag storage memory 3, the microprocessor 1 outputs the address of the main memory 2 to the address bus 6 and accesses the main memory 2. At the same time, the flag is read as a flag state signal 10 from the address in the flag storage memory 3 corresponding to the address in the main memory 2 accessed via the address bus 6, and checked by the flag detection circuit 5.

When the main memory 2 is accessed and the debug trigger address 12 is output to the address bus 6, the flag detection circuit 5 detects the flag, so the flag detection circuit 5 reports it to the microprocessor 1 by the debug notification signal ]1. The microprocessor 1 then proceeds to execute debug processing.

Furthermore, when resetting a flag that has been set in the flag storage memory 2, the flag in the flag storage memory 3 is reset by the flag setting signal 9, similar to the operation for setting the flag described above.

〔Effect of the invention〕

As explained above, the present invention provides a flag storage memory having addresses that correspond one-to-one to the addresses of the main memory,
When the microprocessor accesses a main memory address, the flag is read from the corresponding address in the flag storage memory and checked for the presence or absence of the flag. When a flag is detected, the accessed main memory address is used for debugging. By determining that the address is the one you want to debug, flags can be stored as many times as there are addresses in main memory, so the number of addresses you want to debug can easily be set to the maximum number of addresses in main memory. This has the advantage of not being subject to restrictions such as the number of implemented circuits.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
FIG. 3 is a diagram showing a memory map of a debugging method for the microprogram shown in the figure. 1...Microprocessor, 2...Main memory, 3...Flag storage memory, 4...
... Flag control switch, 5 ... Flag detection circuit, 6 ... Address bus, 7 ... Data bus, 8 ... Hold request signal, 9.
... Flag setting signal, 10 ... Flag status signal, 11 ... Debug notification signal, 12 ...
...Debug trigger address. Agent Patent Attorney Oto Uchihara

Claims (1)

[Scope of Claims] A debugging method for a microprogram including a microprocessor and a main memory for storing a microprogram and data generated by execution of the microprogram, comprising: (A) 1 at each address of the main memory; It has flag storage addresses that correspond to one pair, and when specifying the address in the main memory at which you want to execute debugging, the flag is stored in the flag storage address corresponding to the main memory address, and the flag is stored in the flag storage address corresponding to the main memory address, a flag storage memory from which the flag is removed from the flag storage address when execution is not instructed; (B) flag storage/removal means for storing and removing the flag; (C) the microprocessor from which the address of the main memory is stored; flag detection means that simultaneously reads and checks the flag from an address of the flag storage memory corresponding to the address of the main memory and causes the microprocessor to execute the debugging process when the flag is stored; A microprogram debugging method characterized by having the following features.