JP2626119B2 - Microcomputer development support equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention stores an operating state of a microcomputer while executing the microcomputer in real time without stopping the operation of the microcomputer for debugging a program of the microcomputer system. The present invention relates to a microcomputer development support device.

[Conventional technology]

Conventionally, this type of microcomputer development support apparatus sets an address condition, a data condition, a condition of an external circuit, and the like for stopping the execution of a program (hereinafter referred to as a break condition), and executes the program in real time. When the break condition is satisfied, the microcomputer is stopped. During the execution of the program, all execution states are stored in a history storage memory called a real-time tracer.

[Problem to be Solved by the Invention] The above-described conventional microcomputer development support device employs a method of storing all states regardless of the type of bus state information. In such a case, the microcomputer has an instruction (HALT instruction) to stop its execution while the microcomputer is in the active state, and has a function to stop the execution from an external terminal. No.), a real-time tracer of a microprocessor that repeats a halt state (a bus cycle called a halt state is started.) Writes the halt state to a limited history storage memory, and writes all bus cycles in an execution state to the history. Memory fills up quickly. Normally, even if the history memory is not full, passive bus cycles such as the HALT state are not subject to program debugging, and only one bus cycle is sufficient, many HALT states are stored, and other valid There is a disadvantage that the execution bus cycle cannot be stored.

[Means for solving the problem]

The microcomputer development support apparatus of the present invention has a function for outputting bus state information by a HALT instruction given to the microprocessor and a circuit for decoding the state information output from the microprocessor, and the same state continues at least twice. And a circuit for prohibiting writing to the execution history memory based on the output of the determination circuit.

The microcomputer performs bus state information (hereinafter referred to as bus status) during the execution of a given instruction.
Is output. This bus status is decoded in the external circuit of the microprocessor, and as a result, the CPU is stopped (H
In the case of the ALT state, the processor state is written to the history memory as it is. If the HALT state continues, the second and subsequent writing is prohibited. In this method, a flip-flop that stores the HALT state is provided. First, the flip-flop is set when the HALT bus status is decoded. When the next bus cycle is in the same state, the logic between the decoded signal and the flip-flop is set. This can be realized by taking the product and prohibiting writing. If a new active bus cycle is started in this prohibited state, the prohibited state is released and writing is started.

〔Example〕

 An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a block diagram of the present invention. In FIG. 1, a state information decoding circuit 10, a memory prohibition circuit 11, and a prohibition canceling circuit are added as compared with the conventional microcomputer development support device. First, a simple operation of the development support device will be described. The code to be executed under the control of the supervisor unit 1 is stored in the supervisor bus 6 in the emulation memory 2.
To be stored. The emulation memory 2 and the microcomputer are connected via an emulation processor bus 5, and given to the microcomputer of the instruction code 7 stored in the emulation memory under the control of one supervisor unit, and executed. At this time, in order to stop and suspend the execution of the microcomputer of 7, the break circuit of the stop condition 3 is set in advance,
Execution stops when this condition is met. Since the execution bus state at this time has been output to the emulation processor bus, this information is written into the execution history storage memory 4. At this time, all the bus cycles are written.

In the present invention, the microcomputer 7 capable of outputting the status information 7. (hereinafter referred to as the bus status) is used. When the bus status is in the HALT state, it is identified by the status information decoding circuit 10 and the HALT status continues. Then, writing to the memory is prohibited by the storage enable / disable selection circuit of 11.

2 (a) and 2 (b) are specific circuits and timing diagrams. When the bus status from the microcomputer is (11011), the selector 74LS153 decodes it, recognizes that it is in the HALT state, and sets 74LS74. In the next bus cycle, if the HALT status is output, the clock pulse for 74LS374 write data latch is inhibited.

〔The invention's effect〕

As described above, the microcomputer development support apparatus according to the present invention prohibits the storage of the HALT state for the second time and thereafter by recognizing the microcomputer capable of outputting the state information and the HALT state based on the output information. This makes it possible to effectively use the history storage memory for program debugging in which the HALT state exists for a long time, and to improve the efficiency of program debugging.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1 ... Supervisor section, 2 ... Emulation memory, 3 ... Break circuit, 4 ... Execution history storage memory,
5 emulation processor bus, 6 supervisor processor bus, 7 microcomputer, 8 target system, 9 state information output signal line, 10 state information decoding circuit, 11 state ... A continuous state discriminating circuit, 12... A write prohibition / cancellation circuit FIG. 2 (a) is an example of a state information decoding circuit and a storage enable / disable selection circuit diagram of FIG. 1, FIG. FIG. 3 is a block diagram of an example.

Claims (1)

(57) [Claims] 1. A microcomputer having a function of outputting bus state information indicating an operation state of each bus cycle in a series of bus cycles, and a history of recording the series of bus state information output from the microcomputer. A storage memory and a decoding circuit for decoding the bus state information; and wherein the decoding circuit has an HA
If the LT state is detected, the HALT after the second time
Means for prohibiting writing of a state to the history storage memory, and restarting recording of bus state information in the history storage memory when detecting that the HALT state has been released. Microcomputer development support device.