JPS59158449A - Debugging device - Google Patents

Abstract

PURPOSE:To execute a debug processing program by a CPU of real machine without giving any limitation to an address space of the CPU of real machine by providing a memory for debugging, a jump control circuit or the like. CONSTITUTION:A debug processing program is stored in the memory 3 or debugging of a debug device B and the memory 2 of real machine and a memory 3 are accessed alternatively by the CPU1 of real machine. When a debug processing command is given by a keyboard 5 while the CPU accesses the memory 2 and executes the program of real machine, the command is received and a jump control circuit 7 is activated. That is, the circuit 7 inhibits the memory 2, outputs a head address of the debug processing program of the memory 3 and the program is executed. The debug processing program is executed without giving effect on the address space of the memory 2 in this way by giving forcibly a jump instruction by the circuit 7 and executing the program of the memory 3.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of the Invention) The present invention relates to a debugging device for a combicoater program, and particularly to one that causes a real CPU of a system to be checked to execute a debugging processing program.

(Cost of the Invention) The configuration of a debug device can be divided into two types depending on in which part a debug processing program called a debugger program that performs various signal processing for debugging is executed. One is a configuration in which a debug processing program is executed by a dedicated CPU (microprocessor) provided in a debug device. The other one is a configuration in which the CPU of the system to be checked (this is executed by the actual CP (referred to as J)).

The former device requires a dedicated CPU and is therefore more expensive than the latter device.

The latter debugging device, the conventional one, is a real file CP
A debug processing program converted into a programmable computer is set in a part of the 77 address space of the U. In other words, fruit 11
The debug processing program is allocated to a portion of the address space of 1 CPU that is not used by the program to be checked.

The scale of the program to be checked is small and the actual CPU
If there is sufficient room in the address space, there is no major problem with the conventional method described above. However, if the scale of the program to be checked becomes large, it may become impossible to mount a debug processing program, or even to a lesser extent, careful consideration must be taken to prevent conflicts between the program to be checked and the debug processing program. In other words, this conventional method cannot be applied to the case of Liebe, and is accompanied by various limitations.

(Objective of the Invention) The object of the present invention is to provide a debugging program that has a high degree of freedom, is easy to implement in 414, and is inexpensive, by allowing the debug processing program to be executed by several real CPUs without imposing restrictions on the address space of the real CPU. The goal is to provide equipment.

(Structure and Effects of the Invention) In order to achieve the above objects, the present invention provides a debug memory storing a debug processing program and an actual 111
When a predetermined command is given while the CPU is accessing the real machine memory and executing the program to be checked, the real machine memory is inhibited in synchronization with the instruction code cycle of the real CPU, and this In place of the above debug processing program, a circuit means that gives a jump instruction to the above debug processing program to the actual Di CP LJ, releases the memory for debugging described in -V, and executes the above debug processing program on the actual machine CPU, etc. The present invention includes circuit means for inhibiting the debugging memory for only one specific cycle and unlocking the actual memory in response to a command from the actual CPU by executing a predetermined command. Features.

According to this debugging device, the debug processing program can be installed in a shadow space of the actual CPU's address space instead of being installed in a part of the address space of the actual CPU, and the program to be checked can be installed. It does not have any effect on the address space.

(Description of an Embodiment) FIG. 1 shows an embodiment of the present invention. This figure shows an actual device A to be debugged and a debugging device B according to the present invention combined. However, since the basic configuration of a debugging device that debugs programs by extracting address signals, data bus signals, and control signals from the read terminals or system paths of the actual CPU 1 is well known, detailed illustrations are omitted. are doing. In the figure, only the features of this invention are extracted and shown.

The real machine CPU executes the check target program (this is called the real machine program) stored in the real machine memory 2, but the signal applied to the chip select terminal C8 of the real machine memory 2 is not directly given from the real machine CPU 1. and is given from the debug device 5-B.

The debug device B is connected to the real i via the interface circuit 4.
cI] is coupled to the system bus of U1.

The debug processing program is stored in the memory 3 of the debug device B and executed by the actual CPU 1.

In addition to the debugging memory 3, the debugging device B basically includes a keyboard 5 that is operated by the operator to input 75 types of input necessary for debugging, and a display 6 that displays various information associated with debugging operations. The jump control circuit 7 has a typical configuration and further relates to the gist of the present invention. Actual memory reference control circuit 8 and gate 9
．． It is equipped with inverters 10, 11, etc.

The real machine memory 2 and the debug memory 3 are alternatively accessed by the real machine CPU. A switching signal a output from the gate 9 controls switching between the memories 2 and 3. Signal a is chip select terminal O8 of actual memory 2
A signal obtained by inverting the signal a by an inverter 10 is applied to the chip select 1 terminal O8 of the device 6-lag memory 3. When the signal a is 1 level, the actual memory 2 is enabled and the debug memory 3 is disabled. Conversely, when the signal a goes to L level, the actual memory 2 is disabled and the debug memory 3 is enabled.

When the actual CPU 1 accesses the actual memory 2 and executes the actual program, when a debug processing command is given from the keyboard 5, the jump control circuit 7 operates in response. Kondoki Jump Con 1~[]
As shown in <1) of FIG.
In synchronization with the instruction fetch cycle 1 of ui, the instruction fetch cycle S1 and the first and second operand fetch cycles S3. During the S/I period, an input is given to the gate 9 to set the switching signal a to L level.

During this period, actual memory 2 is prohibited. At the same time, the jump control circuit 7 sends the instruction code of the jump instruction to the system bus of the real IN CPU 1 in the instruction code fetch cycle S1, and also sends the instruction code of the jump instruction to the system bus of the real IN CPU 1 in the instruction code fetch cycle S1, and also sends the instruction code of the jump instruction to the system bus of the real IN CPU 1 in the instruction code fetch cycle S1. .8
During period 4, the start address of the debug processing program in debug memory 3 is output as the jump destination address J-
Ru. Now, the actual CPU 1 executes the jump instruction given from the jump control circuit 7, and thereafter executes the debug processing program in the debug memory 3.

What is meant here is that the address space of the real device memory 2 and the address space of the debug memory 3 may completely overlap. This means that the real machine memory 2 and the debug memory 3 can be used alternatively to create a real 11NcPL.
The point is that it is accessed by J1, and the real 151 CPU that was executing the real machine program in real machine memory 2
1, this is made possible by forcibly giving a jump command through the jump controller 1 to the roll circuit 7 and causing the program in the debug memory 3 to be executed. Therefore,
The debug processing program has no effect on the address space of the real device memory 2 at all.

When executing a debug processing program in the debug memory 3, it is naturally necessary to refer to the data and instructions in the actual memory 2, and to rewrite the data and instructions. This function is realized by the actual memory reference control circuit 8. This control circuit 8 operates in response to a command signal from the real 11cPU1 when the real 11cPU1 executes a reference/update command for the real machine memory 2 in the debug processing program.

The control circuit 8 receives the command signal and operates as shown in FIG.
2), in synchronization with the execution cycle of the load/store instruction of the actual CPU 1, an input signal is applied to the inverter 1 during the reference/update cycle $5, and the input signal is applied to the gate 9.
The switching signal a, which is the output of the switch, is set to the 1'' level. This disables the debug memory 3 and enables the actual memory 2. At this time, the actual memory 2 is accessed by the address signal on the address bus, and its data is read or rewritten. In this way, the debugging operation of the actual machine program is performed.

9-

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a timing chart showing the operation of the debugging device shown in FIG. 1... Actual machine CPU 2... Actual machine memory 3... Memory for debugging 7... Jump control circuit 8... Actual machine memory reference control circuit a... Switching signal Patent applicant Tateishi Electric Co., Ltd. 1 〇－

Claims (1)

[Claims] (1) A device that debugs programs by extracting address signals, data bus signals, and control signals from the read terminals of the actual CPU or the system bus.The debug memory that stores the debug processing program and the actual IICPIJ *machine memory are When a predetermined command is given while the program being accessed and checked is executed, the actual machine memory is inhibited in synchronization with the instruction food fetch cycle of the actual machine CPtJ, and the above debugging is performed on the real machine CPU instead. circuit means for giving a jump command to the processing program and unlocking the debugging memory to execute the debugging processing program on the actual CPU; [Receiving instructions from the CPU,
A debugging device characterized by comprising circuit means for inhibiting the debugging memory and unlocking the actual memory for only one specific cycle.