JPS6152747A - Microprocessor - Google Patents

Abstract

PURPOSE:To select optionally switch operation of a program when instruction fetch is executed by providing a designation address memory circuit, a pseudo instruction generating circuit and a data switching circuit to a microprocessor. CONSTITUTION:When an address is designated to a memory of the designation address memory circuit 10 by a monitor program 5, ''1'', ''0'' is written depending whether the address is the designation address, the designation address is stored in the designation address memory circuit 10, allowing a CPU1 to execute a checked program. The CPU1 fetches the instruction in advance to output an address to an address bus for read of the instruction to be executed next during the execution of the instruction. When the address is the designated address of the memory circuit 10, a data ''1'' is outputted, an instruction to jump to the monitor program 5 unconditionally is generated by the pseudo instruction generation circuit 10, a switching circuit 12 outputs the data of pseudo instruction to a data bus 6 and the monitor program 5 is executed by the CPU1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a microprocessor that operates by prefetching program instructions.

[Conventional technology]

A conventional device of this type is shown in FIG. In the figure, 1 is a CPU (central processing unit) that executes instructions.
, 2 is an address bus that outputs the address of the instruction to be executed by the CPU, 3 is a program memory that stores Fi instructions, 4 is a checked program which is a part of the contents of the program memory 3, and 5t'i is also a monitor program. 6 The output data of the program memory 3 above is converted to C.
A data bus 7 transfers to the PU 1, a specified address 7 specifies the execution of the checked program 4 to be stopped and the start of the monitor program 5, 8 is a specified address 7 that matches the specified address 7 with the address bus 2, and is masked. This is an address match detection circuit that generates an interrupt 9 that cannot be performed.

Next, the operation shown in FIG. 1 will be explained below. Usually, in a microprocessor, a debugging program called a debugging monitor program is executed separately from the checked program.

Here, the monitor program executes and stops the checked program, initializes the checked program, displays the execution results, etc. When the checked program is executed, it stops execution at a specific address and monitors the checked program. To start the program, when an instruction at a designated address is read, a non-maskable interrupt signal is generated for CPU 9, and control of CPU 17 is transferred to the monitor program by this signal. That is, the CPU 1 first outputs the address of the instruction to be executed to the address bus 2, and outputs the instruction of the checked program 4, which is the contents of the address of the program memory 3, to the data bus 6. Next, the CPU 1 reads and executes the instructions on the data bus 6. At this time, an address match detection circuit 8 checks whether the contents of the address bus 2 match the specified address 7, and if the addresses match, a non-maskable interrupt 9 is generated 19 and output to the CPU 1. In this way, the CPU 1i7 accepts the interrupt, executes the read instruction, and then transfers control to the monitor program 5. In this way, the checked program 4 stops execution at the specified address.

Next, the CPU of a microprocessor that prefetches instructions specifies an address, reads an instruction, and executes the instruction in parallel, and reads the instruction several instructions before executing the instruction. There is. Therefore, if the previous read/cancel instruction is a branch instruction, the branch instruction is executed, and execution of the instruction that is already a read is stopped.

In other words, the instructions after the branch instruction are read before the branch instruction is executed, but are not actually executed, so whether or not they are executed after the branch instruction is executed depends on the reading stage of the instruction. Then, it is not confirmed.
In this way, in the case of an address for which execution of the program is not determined at the stage of reading an instruction, execution of the checked program 4 is stopped. To start the monitor program 5, after the control of the CPU 1 is transferred to the monitor program 5, the command at the next specified address 7 is executed from the address at which the checked program 4 stopped. Furthermore, when the checked program 4 is executed by the monitor program 5 until the branch instruction is executed and the instruction at the specified address 7 is executed, it is assumed that the program has stopped at the specified address 7.

If the instruction at the specified address 7 is not executed and the program branches to another address, the monitor program 5Fi causes the checked program 4 to be executed again.

Conventional microprocessors are configured as described above, so in microprocessors that prefetch instructions,
When the specified address at which execution of the checked program is to be stopped occurs after a branch instruction, each time the branch instruction is executed, control is transferred to the monitor program to check whether the instruction at the specified address is executed. become. In addition, if multiple specified addresses are required, detection circuits must be provided for the number of specified addresses required, and since control is transferred to the monitor program for all of the multiple specified addresses, the check target There is a drawback that the program execution time becomes longer by the amount of time the monitor program is executed.

[Summary of the invention]

This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and in the case of a microprocessor that preempts instructions9, it is possible to change the location and number of specified addresses at which execution of the checked program is stopped. Regardless, it is an object of the present invention to provide a microprocessor in which the execution time of the checked program is the same as whether or not program execution can be stopped.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 2, the same parts as in FIG. 1 are shown with the same reference numerals. In FIG. 11 is a pseudo-instruction generating circuit that generates an instruction to unconditionally jump to the monitor program 5 based on the output signal of the specified address memory circuit 10; 12 is a pseudo-instruction generating circuit 11 and the program memory 3; This is a data switching circuit that switches the output of the data bus 6 and outputs the data to the data bus 6.

Next, the operation shown in FIG. 2 will be explained. First, when an address is specified in the memory of the specified address memory circuit 10 by the monitor program 5, if it is the specified address, data 111 is written, and if it is not a specific address, data 101 is written. It is stored and causes the CPU to execute the checked program.

The CPU-j outputs the address of the next instruction to be read to the address bus 2, and then the program memory 3 outputs the instruction of the checked program 4, which is the contents of the address, to the data bus 6 via the data switching circuit 12. Output.

Therefore, the CPU executes the instruction on the data bus 6, but since the microprocessor here preempts the instruction, it reads the next instruction to be executed while the instruction is being executed. The address of the next instruction to be executed is output to bus 2. At that time, address bus 2 causes
Specified address The memory of the memory circuit 10 is specified, and if the above address is the specified address, data 111 is output. Based on the output data 111, a pseudo-instruction to unconditionally jump to the monitor program 5 is generated in the pseudo-instruction generation circuit 10, and the output data of the program memory 3 is generated by the operation of the output data "1" as a pseudo-instruction. The data switching circuit 12 performs an operation for switching with the output data of the generating circuit 11, and outputs the data of the pseudo-instruction generating circuit 11 to the data bus 6. That is, the CPU 1 selects the checked program to be executed from the specified address 7. Instruction 4: A pseudo-instruction is read instead of an instruction.

Next, when the KCPU 1 executes the instruction at the specified address 7, it will execute a pseudo-instruction K, so the control operation is transferred to the monitor program 5.

In this way, the execution of the program to be checked 4#-i is stopped at the specified address, and the same processing as the conventional one is performed.

In addition, although the CPU 1 has read the instruction at the specified address 7, the CPU 1 has read the instruction at the specified address 7, but before executing the instruction, the CPU 1 has read the instruction at the specified address 7, but before executing the instruction,
If the instruction at the specified address 7 is not branched due to the branch instruction from , the read pseudo-instruction is discarded without being executed, and control is not transferred to the monitor program 5.

In the above embodiment, the program to be stopped at a specified address is the checked program, and the program started by a pseudo-instruction is the monitor program, which is used for program debugging. Conversely, by using the monitor program as a change program, another program can be executed at any number of externally specified positions without any change in the normally executed program. Therefore, in the case of the present invention, it can be widely applied as a multiple program switch function using a designated address in the operation of a processor that prefetches instructions.

〔Effect of the invention〕

As described above, according to the present invention, a conventional microprocessor includes a specified address memory circuit, a pseudo-instruction generation circuit,
By adding a data switching circuit and a data switching circuit, it is possible to arbitrarily select the switching operation of a program at a specified address in a microprocessor that prefetches instructions, and the number of instructions This has the advantage that there is no change in execution time.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of the configuration of a conventional microprocessor, and FIG. 2 is a block diagram of a microprocessor circuit configuration in an embodiment of the present invention. 1...CPU, 2...Address bus, 3...Program memory, 4...Checked program, 5...
・Monitor program, 6...Data bus, 7...Specified address, 8...Address match detection circuit, 9...
Interrupts that cannot be masked, 10: designated address memory circuit, 11: pseudo-instruction generation circuit, 12: data switching circuit. In the drawings, the same reference numerals indicate the same or equivalent parts. Figure 2 Procedural amendment (voluntary)

Claims (1)

[Claims] C microprocessor that operates by prefetching instructions
A program memory stores instructions for the PU to execute, and when an instruction at a specified address is read from the program memory, it is accessed at the same address as the program memory, and whether or not addressing is specified is determined by the program. a designated address memory circuit that detects the designated address by writing; a pseudo-instruction generation circuit that generates an instruction to shift execution of an instruction to a specific address based on output data of the designated address memory circuit;
A microprocessor comprising: a data switching circuit that switches output data of the program memory and output data of the pseudo-instruction generation circuit according to output data of the designated address memory circuit, and outputs data to a data bus.