JPS60167038A - Microprocessor - Google Patents

Abstract

PURPOSE:To execute a program to be checked in a time nearly equal to the time when the program is not switched by providing an instruction pre-fetch control system with a pseudo instruction circuit which accesses a specific address with an assigned address. CONSTITUTION:When a CPU1 is allowed to execute the program 4 to be checked, the CPU1 outputs the address of an instruction to be read next to an address bus 2 and program memory 3 outputs the instruction of the program 4 to a data bus 6. When there is the assigned address during the execution of instructions, the pseudo instruction generating circuit 11 generates the specific address, which is outputted to the bus 6 by the switching of a data switching circuit 12. Consequently, the CPU1 accesses the specific address and an interruption generating circuit 13 initiates an interruption which can not be masked to the CPU1, thereby passing the control to a monitor program 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a microprocessor that prefetches instructions and in which, for example, a debugging monitor program is activated by a non-maskable interrupt.

[Prior art]

A typical microprocessor is equipped with a monitor program, also called a depacking program, for checking programs (hereinafter referred to as checked programs).

This monitor program is executed separately from the checked program, and executes, stops, and initializes the checked program, and displays the execution results.

In this case, when executing the program to be checked, in order to stop execution at a specific address and start the monitor program, an unmaskable interrupt is sent to the central processing unit (hereinafter referred to as CPU) when an instruction at the specified address is read. control of the CPH is transferred to the monitor program.

This will be explained in more detail with reference to Figure 1.0 In Figure 1, (1) is the CPU that executes the instruction, and (2) is the address that outputs the address of the instruction that this CPU (1) executes. bus, (8) is a program memory storing instructions, (4) and (5) are a checked program and a monitor program, respectively, which are part of the contents of this program memory (8), and (6) is a program memory ( 3) Output data i CPU (1) Data bus (γ) is a specified address to stop the execution of the checked program (4) and start the monitor program (5), (8) is this address This is an address match detection circuit that detects a match between the specified address (γ) and the contents of the address number (2) and generates all interrupts (9) that cannot be masked.

In FIG. 1, when the CPU (1) outputs the address of an instruction to be executed to the address bus (2), the program memory (8) outputs the instruction of the checked program (4), which is the content of the address, to the data bus (6). ).

At this time, the contents of the address bus (2) and the specified address (
7), and if they match, an interrupt that cannot be masked (9) i CPU (1
). As a result, the CPU (1) accepts this interrupt, executes the read instruction, and then transfers control to the monitor program (6).

Thus, the checked program (4) has stopped execution at the specified address.

By the way, in a microprocessor that preempts instructions, the CPU (1) specifies addresses, reads instructions, and executes instructions in parallel. It is done before the command. At that time, if the previously read instruction is a branch instruction, if this branch instruction is executed, the already read instruction will not be executed.

That is, even if the instructions after the branch instruction are read before the branch instruction is executed, they are not actually executed. Therefore, whether the instruction will be executed or not is not determined at the 9th step of reading the instruction.

In this way, in order to stop the execution of the checked program (4) and start the monitor program (5) at an address whose execution is not determined at the 9th step of reading the instruction, the CPU
After the control of (1) is transferred to the monitor program (6), the monitor program (5) continues to control the checked program (4) from the address where the checked program (4) stopped until the specified address or branch instruction is executed. If the instruction at the specified address is executed, it is assumed that the program has stopped at the specified address, and if the instruction at the specified address is not executed and the program branches to another address, the monitor program (5 ) causes the checked program (4) to be re-executed.

However, in conventional microprocessors that prefetch instructions, when the specified address at which the execution of the checked program is to be stopped occurs after a branch instruction, the monitor program is It is necessary to check whether control is transferred and the instruction at the specified address is executed, and if multiple specified addresses are required, a corresponding number of detection circuits are required to detect these specified addresses. Since control is transferred to the monitor program for all of the above, there is a drawback that the execution time of the checked program becomes longer by the amount of execution of the monitor program.

[Summary of the invention]

The present invention was made for the purpose of eliminating the above-mentioned drawbacks.
In a microprocessor that preempts an instruction, when an instruction at a specified address is read from the program memory, it is accessed at the same address as this program memory, and the specified address is read by writing the presence or absence of the instruction to the program memory. A specified address memory circuit to be detected, a pseudo-instruction generation circuit that generates an instruction for accessing a specific address by the output of this specified address memory circuit, and output data of this pseudo-instruction generation circuit and output data of the program memory as described above. A data switching circuit that outputs data to a data bus by switching depending on the output of a specified address memory circuit, and an interrupt generation circuit that generates an interrupt that cannot be masked to a CPH when the specific address is accessed. The present invention proposes a microprocessor that can execute a checked program in approximately the same time as when execution is not stopped, regardless of the location and number of specified addresses at which execution of the checked program is stopped.

[Embodiments of the invention]

FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention, and in the figure, the same reference numerals as in FIG. 1 indicate the same elements. Then, a specified address memory circuit αQ is accessed at the same address as the program memory (8) and detects this specified address by writing the presence or absence of the specification into the program, and a specific address is detected by the output of this specified address memory circuit θ0). Pseudo-instruction generation circuit that generates instructions for access (
111 and a data switching circuit (old) that switches between the output data of this pseudo-instruction generation circuit (Ill and the output data of the program memory (8) and outputs it to the data bus (6)), and a new In place of the address match detection circuit (8) shown in the figure, an interrupt generation circuit (13) is provided which generates all interrupts (9) that cannot be masked when a specific address is accessed.

The operation of the microprocessor configured as described above will be explained below.

First, the monitor program writes data rIJ'e into the specified address memory circuit if the address is the specified address, and data "0" if the address is not the specified address.

Then, when the CPU (1) executes the checked program (4), the CPU (1) outputs the address of the next instruction to be read to the entire address bus (2), and the program memory (8) stores the address of that address. The command of the checked program (4), which is the content, is output to the data bus (6) via the data bus switching circuit.

As a result, the CPU (1) uses 11 of the data bus (6).
However, since this microprocessor prefetches instructions, it reads the next instruction to be executed while the instruction is being executed.

outputs the address to address bus (2).

At this time, the address bus (2) specifies the memory of the specified address memory circuit OQ, and if the address is the specified address, data "1" is output. This data "1" causes the pseudo-instruction generation circuit C11 to generate a pseudo-instruction to access a specific address, and also generates a pseudo-instruction that accesses a specific address.
”, the data switching circuit (L?J is the program memory (
The output data of 8) is switched to the output data of the pseudo-instruction generation circuit (Ill) and output to the data bus (6).

In other words, the CPU (1) reads a pseudo-instruction from the specified address (γ) instead of the instruction of the checked program (4) to be executed.Next, the CPU (1) will execute the instruction at the specified address. If so, a pseudo-instruction will be executed and a specific address will be accessed, and the interrupt generation circuit (12
) adds a non-maskable interrupt to CPU (1). Then, the CPU (1) accepts this interrupt and transfers control to the monitor program (5).

As a result, the checked program (4) has stopped execution at the specified address, and the same processing as the conventional device can be performed.By the way, even if the instruction at the specified address is read, The checked program (4
) When the instruction at the specified address is branched by a branch instruction, the read pseudo-instruction is discarded without being executed, so control is never transferred to the monitor program.

In the above embodiment, the program to be checked is a program to be stopped at a specified address, and the program started by an interrupt that cannot be masked is used as a monitor program to debug the program.
By using the monitor program as a change program, you can make the normally running program run at any number of arbitrary positions specified from the outside without changing the normal program. The invention is broadly applicable to multiple program switches at specified addresses in processors performing instruction prefetching.

〔Effect of the invention〕

As is clear from the above explanation, according to the present invention, when performing a program switch at a specified address, the number of switch locations can be arbitrarily selected, and the checked program can be executed in approximately the same time as when no switch is performed. Excellent effects have been obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a conventional microprocessor, and FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention. (1) Central processing unit (2) Address bus (8) Program memory (4) e Checked program (5) Monitor program (6) Data bus (7) Fist・Specified address (8)
- Address matching circuit (9) e - Interrupt call that cannot be masked - Specified address memory circuit (11) φ - Pseudo-instruction generation circuit (mausoleum... data switching circuit OB) @ - Interrupt generation circuit Note that the same reference numerals are used in the diagram. indicate the same or equivalent part. Agent Masuo Oiwa Figure 1 Figure 2 Procedure Amendment (Voluntary) 1. Indication of the case Patent application Sho # -z, 3z / number 2, name of the invention microprocessor 3, person making the amendment representative Hitoshi Katayama department 4, agent 6, statement of contents of amendment page 11 line 17 The description "(8) . . . address matching circuit" is corrected to "(8) . . . address matching detection circuit."that's all

Claims (1)

[Claims] When an instruction at a specified address is read from the program memory in a microprocessor that is performing instruction prefetching (#), it is accessed at the same address as this program memory, and the presence or absence of the instruction is specified by writing it into the memory by the program. A specified address memory circuit that detects an address, a pseudo-instruction generation circuit that generates an instruction to access a specific address by the output of this specified address memory circuit, and output data of this pseudo-instruction generation circuit and output data of the program memory. and an interrupt generation circuit that generates an interrupt that cannot be masked to the central processing unit when the specific address is accessed. Features a microprocessor.