JPH0895946A - Microcomputer - Google Patents

Abstract

PURPOSE: To enable a microcomputer to perform a normal operation by executing a correction program when a bug exists in a program on an incorporated ROM by performing control so as to supply a branch instruction to an instruction queue when a prefetch address to be outputted for prefetching an instruction is coincident with the contents of a register. CONSTITUTION: When a bug exists in the program on a ROM 3, a CPU 7 continuously executes the program on the ROM 3 until a fetch pointer 1 reaches the leading address of the bug part. When the fetch pointer 1 arrives at the leading address of the bug part, namely, when the contents of the fetch pointer 1 and a register 6 are coincident with each other, a comparator circuit 5 outputs a high-level select signal 12 and a selecting circuit 8 receives the select signal 12, switches the program on the ROM 3 to the output of a branch instruction output circuit 9 and outputs the branch instruction to an instruction queue 15. The CPU 7 receives the branch instruction from the instruction queue 15 and executes it.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing device, and more particularly, to a CPU for performing arithmetic and control on a single semiconductor substrate,
A program memory for storing a program, said C
A fetch pointer indicating the address on the program memory of the instruction to be fetched in the PU, an interface means for fetching data from the outside, and an instruction queue for prefetching (prefetching) and storing the instruction to be executed by the CPU thereafter. The present invention relates to an integrated microcomputer.

[0002]

2. Description of the Related Art A microcomputer is an integrated circuit in which a CPU for arithmetic and control and peripheral circuits such as a memory and a timer are contained on one chip and is used in various fields such as home electric appliances and OA equipment.

A program for controlling the microcomputer is usually written in a read-only memory circuit called a mask ROM. The program is written in the mask ROM in the manufacturing process of the microcomputer, and its contents cannot be changed after manufacturing.

Therefore, if a bug is found in the program after the user receives the product, the contents of the program cannot be rewritten, and all the products are wasted, and the order and the manufacturing process are repeated. It will have to be done. If a microcomputer is installed in a home electric appliance or the like, which produces a huge number of products per month, the damage will be enormous.

In order to avoid this enormous damage, Japanese Patent Application No. 5-215616 filed by the same applicant as the present invention.
In order to provide a microcomputer capable of executing a corrected program by avoiding execution of an address having a bug in the program after manufacturing the microcomputer, the following method is proposed. .
This will be described below as a conventional example.

FIG. 5 is a block diagram showing a schematic configuration of a microcomputer proposed in Japanese Patent Application No. 5-215616.

Referring to FIG. 5, program counter 23
Is a counter that sequentially indicates the addresses at which the instructions to be executed by the CPU 24 are stored. The ROM 3 is a read-only memory in which a program is written and is connected to the address bus 2 and the data bus 11. Address data is sent to the address bus 2, and the data bus 11 transfers the data.

The RAM 4 is a readable / writable memory and is connected to the address bus 2 and the data bus 11. The serial interface 10 is connected to the memory 14, the data bus 2, and the address bus 11, fetches data from the memory 14 and sends the data to the data bus 11.

The memory 14 arranged outside the microcomputer 25 stores the start address of the bug part of the program and the correction program.

The register 6 is a memory circuit for storing the head address data of the bug part. Comparison circuit 5
Compares the content of the content program counter 23 with the content of the register 6 and outputs a selection signal 12 which is set to a high level when they match and is set to a low level when they do not match.

The branch instruction output circuit 9 outputs a branch instruction to the start address of the correction program stored in the RAM 4 to the selection circuit 8. The selection circuit 8 receives the selection signal 12 and outputs the branch instruction from the branch instruction output circuit when the selection signal 12 is at the high level, and outputs the program on the ROM 3 or RAM 4 to the CPU 24 when the selection signal 12 is at the low level. C
The PU 24 decodes / executes the input instruction, thereby executing the program.

Next, referring to FIG. 5, Japanese Patent Application No. 5-215
The operation of the microcomputer proposed in No. 616 will be described.

First, at the time of system initialization, the head address data of the bug portion is set in the register 6 from the memory 14 via the serial interface 10, and the correction program is loaded into the RAM 4.

The program on the ROM 3 is executed by the CPU 24, and the program counter 23 is counted up at the same time.

When the contents of the program counter 23 match the start address of the bug portion set in the register 6, the comparison circuit 5 outputs the high-level selection signal 1
2 is output, and the selection circuit 8 stops the transfer of the program on the ROM 3 or RAM 4 to the CPU 24, and transfers the branch instruction from the branch instruction output circuit 9 to the CPU 24.

The CPU 24 executes the branch instruction from the branch instruction output circuit 9, and the program counter 23 makes the RAM 4
Set to the top address of the above fix, CP
U24 will run the fix.

Then, at the last part of the modification program,
By inserting a branch instruction to the address after the bug part, it is possible to return to the original program.

By such a method, the bug portion of the program stored in the ROM 3 can be avoided, the correction program on the RAM 4 can be executed, and the bug can be corrected.

[0019]

In recent years, various design methods for improving the processing speed of a microcomputer have been developed and used, and one of them is a method using an instruction queue.

In a normal microcomputer, the CPU
The processes of fetching instructions, decoding instructions, and executing instructions were sequentially performed. For this reason, the time required to fetch an instruction occupies a relatively large proportion in the instruction execution time.

Therefore, the CPU is provided with an instruction queue (also referred to as "instruction buffer" or "prefetch queue") composed of a memory circuit capable of storing a plurality of instructions between the instruction fetching step and the instruction decoding step. And CPU
Preempts the next instruction by effectively utilizing the free time of the bus while decoding and executing one instruction
And store it in the instruction queue.

As a result, the CPU can execute the next instruction stored in the instruction queue immediately after the execution of one instruction is completed, and the time for fetching the instruction into the CPU can be shortened. . That is, the execution cycle of one instruction and the instruction fetch cycle of another instruction are overlapped and pipelined.

Therefore, by adopting this instruction queue, C
The instruction execution speed of the PU has increased, and the processing speed of the microcomputer has significantly improved.

However, in the microcomputer having the instruction queue, there is a problem that the conventional example cannot be used. The reason will be described in detail below.

If the conventional example is used as it is, at the time when the program counter reaches the start address of the bug portion, some prefetched (prefetched) instructions are already fetched in the instruction queue. , Of course, the bug part is also preempted and included in it.

Therefore, the branch instruction is taken into the instruction queue after the instruction of the bug portion, and the CPU executes the branch instruction after executing the bug portion.
Therefore, execution of the bug part cannot be avoided.

Further, when the program counter reaches the start address of the bug part, instead of from the instruction queue,
If the signal from the branch instruction output circuit is directly input to the CPU, the execution of the bug part is surely avoided, but this method is provided because the instruction queue is provided in the CPU to increase the processing speed of the CPU. In order to realize the above, a major modification of the CPU is required.

In a microcomputer, the CPU is the most important circuit unit and is the base portion, so if there is a circuit defect, it is not desirable to modify it.

Therefore, it is preferable to add the function of the microcomputer by adding or changing the peripheral circuit instead of modifying the CPU itself.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a built-in ROM in a ROM built-in microcomputer having an instruction queue for prefetching instructions. If there is a bug in this program, by avoiding the execution of the bug part and executing the alternative program,
It is to provide a microcomputer that can operate normally.

[0031]

According to the present invention, the object is to store predetermined address information in a microcomputer including at least an instruction queue for storing prefetched instructions and a ROM for storing a program. Register and a branch instruction output unit for outputting a predetermined branch instruction, and when the prefetch address output for prefetching the instruction matches the content of the register, the branch instruction is added to the instruction queue. This is achieved by a microcomputer characterized by controlling to supply a branch instruction output from an output unit.

The present invention is characterized in that a value is externally set in the register.

Further, in another aspect of the present invention, the branch instruction output unit includes a branch destination address register for storing a branch destination address in the branch instruction, and a value is externally set in the branch destination address register. It is characterized by being configured as described above.

The present invention, in a preferred embodiment,
CPU for arithmetic and control, program memory for storing programs, and CP on a single semiconductor substrate
A microcomputer in which a fetch pointer indicating an address on the program memory of an instruction to be fetched in U, an interface means for fetching data from the outside, and an instruction queue in which the CPU stores an instruction to be executed thereafter is integrated. In the storage means for storing predetermined address information fetched from the outside of the microcomputer through the interface means, the address information stored in the storage means and the contents of the fetch pointer are compared, and based on the comparison result. Comparing means for outputting a selection signal, branch instruction output means for outputting a branch instruction for changing the address of the program to be executed by the CPU, the branch instruction when the selection signal is true, and the branch instruction when the selection signal is false Selection means for outputting the contents of the program memory to the instruction queue When the CPU executes the program on the program memory and the address information of the storage means fetched via the interface means and the content of the fetch pointer match, the CPU is A microcomputer configured to execute a branch instruction output from the branch instruction output means to change an address to be executed next by the CPU.

As another preferred embodiment of the present invention, a CP for performing calculation and control on a single semiconductor substrate.
U, a program memory for storing a program, a fetch pointer indicating an address on the program memory of an instruction to be fetched in the CPU, an interface means for fetching data from the outside, and an instruction to be executed by the CPU from the next time onward. In a microcomputer in which instruction queues are accumulated, a plurality of storage means for storing a plurality of predetermined address information fetched from the outside of the microcomputer through the interface means, contents of the plurality of storage means and the fetch pointer And one or a plurality of comparison means for outputting one or a plurality of selection signals based on the result, and one or a plurality of branch instructions for changing the address of the program to be executed by the CPU. One or more branch instruction output means for outputting, and the selection signal Selection means for outputting the content of the program memory to the instruction queue when all are false, and for outputting a branch instruction from one branch instruction output means selected by the selection signal otherwise. When the CPU executes the program on the program memory and the address information of any one of the plurality of storage means fetched via the interface means and the content of the fetch pointer match, the CPU Executes the branch instruction from the selected branch instruction output means,
There is provided a microcomputer configured such that the CPU changes an address to be executed next.

According to another aspect of the present invention, in a preferred mode, a CPU for performing calculation and control, a program memory for storing programs, and a program memory for instructions to be stored in the CPU are provided on a single semiconductor substrate. In a microcomputer in which a fetch pointer indicating an address, an interface means for fetching data from the outside, and an instruction queue for storing an instruction to be executed by the CPU afterward are integrated, the microcomputer is externally provided via the interface means. A correction address storage unit for storing the correction address information and the branch destination address information fetched from the storage unit provided, and a branch destination address storage unit are provided, and further, the correction address storage unit and the fetch pointer. Compare the contents of and the ratio Comparing means for outputting a selection signal based on the result; branch instruction outputting means for outputting a branch instruction for changing the address of the program to be executed by the CPU to the contents of the branch destination address storing means; Selection means for outputting the branch instruction when true and outputting the contents of the program memory to the instruction queue when false, and the interface means for the CPU to execute the program on the program memory. When the corrected address information of the corrected address storage means fetched via the register and the contents of the fetch pointer match, the CPU executes a branch instruction to the address in the branch destination address storage means, and the CPU executes the next instruction. A microcomputer configured to change an address to be executed in .

Further, in another preferred embodiment of the present invention, a CP that performs calculation and control on a single semiconductor substrate.
U, a program memory for storing a program, a fetch pointer indicating an address on the program memory of an instruction to be fetched in the CPU, an interface means for fetching data from the outside, and an instruction to be executed by the CPU from the next time onward. A plurality of modified address storages for storing a plurality of modified address information and a plurality of branch destination address information fetched from storage means outside the microcomputer via the interface means Means and a plurality of modified address storage means, and further,
One or a plurality of comparing means for comparing the contents of the plurality of modified address storage means and the contents of the fetch pointer and outputting one or a plurality of selection signals based on the result, and the address of the program to be executed by the CPU as the branch destination. One or a plurality of branch instruction output means for outputting a branch instruction for changing to the contents of the address storage means, the contents of the program memory when the plurality of selection signals are all false, and the selection signal otherwise. Selection means for outputting the branch instruction from the branch instruction output means selected in step 1 to the instruction queue, and the CPU fetches it via the interface means when executing the program on the program memory. If the correction address information of any one of the plurality of correction address storage means and the content of the fetch pointer match, A micro-processor, wherein a CPU executes a branch instruction to an address of a branch-destination address storage means selected from the plurality of branch-destination address storage means, and the CPU changes an address to be executed next. Provide a computer microcomputer.

[0038]

According to the present invention, the address information of the bug portion is given to the register from the outside, and when the content of the fetch pointer matches the content of the register in the process of executing the program, it is predetermined by the selection circuit. By transferring a predetermined branch instruction to the instruction queue and executing the branch instruction by the CPU, the execution of the bug portion is avoided, the correction program stored in advance at another address is executed, and the execution of the bug portion is executed. Avoided.

According to another aspect of the present invention, a branch destination address whose value can be arbitrarily set externally is provided, and the external RO
Since it is not necessary to load the modification program from M into the microcomputer, the program initialization routine only needs to set the bug start address and branch destination address in each register, which simplifies the program and reduces the size and fetches it. Since the branch destination address can be set freely when the pointer reaches the bug part, the restrictions on the memory position and size of the program and the modification program are greatly relaxed, and the degree of freedom in design is increased.

Further, in the present invention, preferably, the microcomputer is provided with a plurality of registers and a plurality of branch instruction generation circuits, so that different corrections can be made in response to a plurality of bugs.

[0041]

Embodiments of the present invention will be described below with reference to the drawings.

[0042]

First Embodiment FIG. 1 is a block diagram showing the structure of the first embodiment of the present invention.

Referring to FIG. 1, the fetch pointer 1 is
It is a 16-bit counter indicating the address of the program to be fetched from the ROM 3 or RAM 4 into the instruction queue 15. The address bus 2 is a 16-bit bus for transferring address data and the data bus 11 is a 16-bit bus for transferring data.

The ROM 3 is a read-only memory and has addresses 0000H to EFFFH (H represents a hexadecimal number).
Corresponding to the memory space of, where the program is stored. The RAM 3 is a readable / writable memory and has an address F.
It corresponds to a memory space of 000H to EFFFH.

The head address of the bug portion and the correction program are stored in the memory 14 arranged outside.

The serial interface 10 is the memory 1
The start address of the bug part in 4 and the correction program are loaded into the microcomputer 13.

The register 6 is a serial interface 1
0 and the head address of the bug portion fetched via the data bus 11 is stored and stored.

The comparison circuit 5 compares the contents of the register 6 and the contents of the fetch pointer 1 input via the address bus 2, and if they match each other, it is set to a high level and does not match. If so, the selection signal 12 that is at a low level is output.

The branch instruction output circuit 9 outputs a branch instruction to the address F000H on the RAM 4.

The selection circuit 8 outputs the branch instruction from the branch instruction output circuit 9 to the instruction queue 15 when the selection signal 12 from the comparison circuit 5 is high level (= active), and the selection signal 12 is low level (= active). When inactive), the program on the ROM 3 or RAM 4 is loaded into the instruction queue 1
5 is output.

The instruction queue 15 is a 5-byte buffer that stores instructions prefetched while the CPU 7 is executing the instructions.

The CPU 7 takes out an instruction from the instruction queue 15 and decodes the instruction by an instruction decoder unit (not shown) and executes the decoded instruction by an execution unit (not shown).

Next, in the present embodiment, when a program on the ROM 3 has a bug, the operation principle for avoiding the bug will be described.

Here, as shown in the memory map of FIG. 2, the program has addresses 1000H to 7 on the ROM 3.
Exists in FFFH, of which addresses 4000H-40
Assume there is a bug at 0FH.

Further, referring to FIG. 2, the program start address 1000H is set in the vector table 0000H for setting the program start address, and as a result, the address 1000H is set after the reset release of the microcomputer 13. The fetch pointer 1 is set, and execution of the program is started from the address 1000H.

In advance, assuming that a bug exists, the serial interface 1 is provided in the initialization part of the program.
A routine for loading the start address of the bug portion and the correction program from the memory 14 into the microcomputer 13 via 0 is inserted.

By executing this initialization part, the start address 4000H of the bug part and the correction program are loaded from the memory 14 into the microcomputer 13, and the start address of the bug part loaded into the microcomputer 13 is set in the register 6. Further, the correction program is stored in the RAM 4 at and after the address F000H.

After that, the CPU 7 continues to execute the program on the ROM 3 until the fetch pointer 1 reaches the start address of the bug part.

When the fetch pointer 1 reaches the start address of the bug part, that is, the fetch pointer 1
And the contents of the register 6 match each other, the comparison circuit 5
Outputs a high-level selection signal 12, and the selection circuit 8 receives the selection signal 12 and switches from the program on the ROM 3 to the output of the branch instruction output circuit 9, and outputs the branch instruction to the instruction queue 15.

Here, the branch instruction output circuit 9 determines the address F
In order to output the branch instruction “BR! F000H” to 000H, the CPU 7 receives the branch instruction from the instruction queue 15 and executes it.

Generally, the contents of the instruction queue are configured to be cleared by executing a branch instruction, and the contents of the instruction queue 15 are cleared by a manual folding or branch instruction. Further, the fetch pointer 1 is set to F000H, and the correction program on the RAM 4 is executed by the CPU 7, as shown in FIG.

By inserting the branch instruction "BR! 4010H" to the address 4010H in the last portion of the modification program, the original ROM is executed after the modification program is executed.
Returning to the program above 3, the original program will be executed.

According to the above procedure, the addresses F000H to F0 on the RAM 4 are executed without executing the bug part of the addresses 4000H to 400FH of the program on the ROM 3.
Execute the correction program of 1FH, then ROM3 again
You can run the above program.

According to this embodiment, even if a bug occurs in the program on the ROM 3 of the microcomputer, it is possible to correct the bug. Therefore, it is possible to effectively use these microcomputers without discarding them. It is possible and avoids loss.

In this embodiment, since the program size of the correction program is not fixed, it can be used not only for correcting the bug but also for adding a new program.

[0066]

Second Embodiment Next, a second embodiment of the present invention will be described. FIG. 3 is a block diagram showing the configuration of the second embodiment of the present invention. In FIG. 3, elements having the same functions as those in FIG. 1 are designated by the same reference numerals.

In this embodiment, the present invention is applied to a microcomputer having an external memory area. That is, the microcomputer according to the present embodiment is configured to be able to access the external memory through the port and set the branch destination of the branch instruction in all memory spaces.

Only the differences between this embodiment and the first embodiment will be described below. Referring to FIG. 3, external ROM
Reference numeral 21 is a memory writable by the user by using a dedicated device, and is a port 1 through the external bus 20.
9 is connected. The memory space of the external ROM 21 is
The addresses are 8000H to FFFFH (see FIG. 4).

The external bus 20 is a 16-bit wide bus. The port 19 sends the address signal received from the address bus 2 to the external ROM 21 and outputs the data received from the external ROM 21 to the data bus 11.

The branch destination address register 18 is a memory circuit for setting the branch destination address of the branch instruction output from the branch instruction output circuit 17, and by providing this circuit, it is possible to branch to an arbitrary address. become.

Next, the operation of this embodiment will be described.
FIG. 4 shows a memory map of the microcomputer according to this embodiment.

Referring to FIG. 4, the microcomputer 2
In the memory space of No. 2, the program is the address 1000H to 7FFFH of the ROM 16 and the external ROM 21.
Are stored at addresses 8000H to AFFFH.

The bug portion is assumed to exist at the addresses 4000H to 400FH of the ROM 16, and the correction program for correcting the bug portion is stored at the addresses C000H to C02FH on the external ROM 21, and the head address data of the bug portion is stored. "4000H" is an external ROM
Addresses on F21 from F000H to F001H (2 bytes)
Further, it is assumed that the branch destination address data “C000H”, which is the start address of the correction program, is stored in the addresses F002H to F003H on the external ROM 21.

First, in the program initialization routine, the data of the bug part start address and the branch destination address on the external ROM 21 are transferred to the register 6 and the branch destination address register 18 via the port 19, respectively.

As a result, the bug start address "4000H" is set in the register 6, and the branch destination address data "C000H" is set in the branch destination address register 18.

Then, the normal program is executed,
When the fetch pointer 1 reaches 4000H, the branch instruction from the branch instruction output circuit 17 is fetched into the instruction queue 15.

The branch instruction at this time is "BR! C00" according to the contents of the branch destination address register 18 set previously.
0H ”(branch instruction to address C000H).

By executing this branch instruction, the CPU 7 executes the correction program after the address C000H as shown in FIG. Then, at the end of the fix, "BR! 4010H" (address 4
A branch instruction to 010H) is inserted so that the program on the original ROM 16 is executed after the correction program is executed.

By the above method, the bug part of the program can be avoided and the correction program can be executed in the microcomputer having the external ROM.

According to the second embodiment of the present invention, the external RO
Since the modification program does not have to be loaded into the microcomputer from M, the program initialization routine is simplified, and the branch destination address can be set freely when the fetch pointer reaches the bug part. It increases the degree of freedom in designing the memory location and size.

Also, in the second embodiment of the present invention,
Since the program size of the correction program is not fixed, it can be used not only to deal with the bug correction but also to add a new program.

In each of the above-described embodiments, the description has been made based on the configuration in which the one register 6 and the one branch instruction generating circuit 9 are provided in the microcomputer, but a plurality of registers for storing the bug start address are provided and It goes without saying that a plurality of branch instruction output circuits 9 for outputting the branch instruction destination address corresponding to the above may be provided. In this case, the comparison circuit 5 compares the contents of the fetch pointer 1 with the contents of a plurality of registers, and the output of the branch instruction output circuit corresponding to the register having the matched contents is output via the selection circuit 8. With this configuration, it is possible to make different corrections for a plurality of bugs.

Although the present invention has been described with reference to the above embodiments, the present invention is not limited to the above embodiments, but includes various embodiments according to the principle of the present invention. For example, the microcomputer and the memory map in which the address and the data are 16 bits described in the above embodiments should be construed as merely for facilitating the understanding of the present invention. Of course, it can be similarly applied to a 32-bit microcomputer or the like.

[0083]

As described above, the present invention described in each claim has the following effects.

Even if a bug occurs in the program on the ROM of the microcomputer, it is possible to correct the bug. Therefore, it is possible to effectively use those microcomputers without discarding them, and avoid loss. .

Further, even if the debugging is not complete and there is a possibility that a bug exists in the program, it is possible to fix it later, so that the ordering of the microcomputer can be made without fear of serious damage.

Further, since the size of the correction program is not fixed, the present invention can be utilized not only for correcting the bug but also for adding the program.

According to the present invention (claims 2, 6, and 9), the value specified in the register designated by the bug start address is externally set via the interface or port, and the bug occurrence location is set. Corresponding and appropriate measures can be taken.

Another aspect of the present invention (claims 3 and 7).
According to this, since it is not necessary to load the correction program from the external ROM into the microcomputer, the initialization routine of the program is simplified. In addition, the branch destination address when the fetch pointer reaches the bug part can be set freely, so the restrictions on the memory position and size of the program and the modification program are relaxed, and the degree of freedom in design is increased, so that the program design is improved. It will be easier.

Furthermore, according to the present invention (claims 5 and 8), a plurality of registers and branch instruction generation circuits are provided in the microcomputer, so that a plurality of bugs can be prevented.
You will be able to make different modifications.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a microcomputer according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a memory map of the microcomputer according to the first embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a microcomputer according to a second embodiment of the present invention.

FIG. 4 is a memory map of the microcomputer according to the second embodiment of the present invention.

FIG. 5 is a block diagram showing an example of a configuration of a microcomputer according to a prior art.

[Explanation of symbols]

 1 Fetch Pointer 2 Address Bus 3, 16 ROM 4 RAM 5 Comparison Circuit 6 Register 7, 24 CPU 8 Selection Circuit 9, 17 Branch Instruction Output Instruction 10 Serial Interface 11 Data Bus 12 Selection Signal 13, 22, 25 Microcomputer 14 Memory 15 Instruction queue 18 Branch destination address register 19 Port 20 External bus 21 External ROM 23 Program counter

Claims (9)

[Claims] 1. A microcomputer including at least an instruction queue for storing prefetched instructions and a ROM for storing programs, a register for storing predetermined address information, and a branch instruction output for outputting a predetermined branch instruction. And a control unit for supplying a branch instruction output from the branch instruction output unit to the instruction queue when the prefetch address output for prefetching the instruction matches the content of the register. A microcomputer characterized by: 2. The microcomputer according to claim 1, wherein a value is externally set in the register. 3. The branch instruction output unit includes a branch destination address register for storing a branch destination address in a branch instruction, and a value is set to the branch destination address register from the outside. The microcomputer according to claim 1 or 2. 4. A CPU for computing and controlling, a program memory for storing a program, a fetch pointer indicating an address on the program memory of an instruction to be fetched into the CPU, and a data externally fetched on a single semiconductor substrate. Interface means and CPU
Is an instruction queue that stores the instructions to be executed afterwards,
In a microcomputer integrated with, storage means for storing predetermined address information fetched from the outside of the microcomputer through the interface means, comparing the address information stored in the storage means and the content of the fetch pointer, A comparison unit that outputs a selection signal based on the comparison result, a branch instruction output unit that outputs a branch instruction for changing the address of the program to be executed by the CPU, and a branch instruction when the selection signal is true. Selecting means for outputting the contents of the program memory to the instruction queue when false, the CPU fetching via the interface means when the CPU executes the program on the program memory. The address information of the storage means and the content of the fetch pointer match. If the CPU is running a branch instruction output from the branch instruction output unit, the C
A microcomputer configured such that the PU changes the address to be executed next. 5. A single semiconductor substrate on which a CPU for arithmetic and control, a program memory for storing a program, a fetch pointer indicating an address on the program memory of an instruction to be fetched in the CPU, and a data fetched from the outside. Interface means for storing a plurality of predetermined address information fetched from the outside of the microcomputer through the interface means in a microcomputer in which an instruction queue for storing instructions to be executed by the CPU thereafter is integrated. Execution of the plurality of storage means, one or a plurality of comparison means for comparing the contents of the plurality of storage means with the contents of the fetch pointer and outputting one or a plurality of selection signals based on the result, and the CPU One or more branches to change the address of the program to be executed One or more branch instruction output means for outputting a command, and outputs the contents of the program memory to the instruction queue when the selection signals are all false, and one branch selected by the selection signal otherwise. Selecting means for outputting a branch instruction from the instruction output means, and any one of the plurality of storage means fetched via the interface means when the CPU executes the program on the program memory. When the address information of one and the contents of the fetch pointer match, the CPU executes the branch instruction from the selected branch instruction output means, and the CPU changes the address to be executed next. A microcomputer characterized by being configured in. 6. The microcomputer according to claim 4, further comprising a port for exchanging data with a storage device external to the microcomputer instead of the interface means. 7. A single semiconductor substrate is provided with a CPU for computing and controlling, a program memory for storing a program, a fetch pointer indicating an address on the program memory of an instruction to be loaded into the CPU, and data from outside. Interface means for storing a command queue for storing instructions to be executed by the CPU thereafter, and a modified address fetched from a storage means provided outside the microcomputer via the interface means. And a branch destination address storage unit for respectively storing the information and the branch destination address information, further comparing the contents of the correction address storage unit and the fetch pointer, and based on the comparison result. A comparison means for outputting a selection signal, Branch instruction output means for outputting a branch instruction for changing the address of the program to be executed by the CPU to the contents of the branch destination address storage means; the branch instruction when the selection signal is true, and the program when the selection signal is false Selecting means for outputting the contents of the memory to the instruction queue, and the correction address of the correction address storage means fetched via the interface means when the CPU executes the program on the program memory. If the information and the contents of the fetch pointer match, the C
A microcomputer configured such that a PU executes a branch instruction to an address in the branch destination address storage means, and the CPU changes an address to be executed next. 8. A single semiconductor substrate, a CPU for performing calculation and control, a program memory for storing a program, a fetch pointer indicating an address on the program memory of an instruction to be loaded into the CPU, and a data externally loaded. A plurality of modified address information and a plurality of correction address information fetched from a storage means external to the microcomputer via the interface means, A plurality of modified address storage means and a plurality of modified address storage means for respectively storing the branch destination address information, and further comparing the plurality of modified address storage means with the contents of the fetch pointer, and based on the result. Outputs one or more selection signals One or a plurality of comparing means; one or a plurality of branch instruction outputting means for outputting a branch instruction for changing the address of the program to be executed by the CPU to the content of the branch destination address storing means; Selecting means for outputting the content of the program memory when all the signals are false, and for outputting the branch instruction from the branch instruction output means selected by the selection signal to the instruction queue otherwise. When executing the program on the program memory, if the correction address information of any one of the plurality of correction address storage means fetched via the interface means and the contents of the fetch pointer match, The CPU executes a branch instruction to the address of the branch destination address storage means selected from the plurality of branch destination address storage means. Then, the CPU changes an address to be executed next time, the microcomputer. 9. The microcomputer according to claim 7, further comprising a port for exchanging data with a storage device external to the microcomputer, instead of the interface means.