CN118132427A - Chip operation tracking method, chip, board card, electronic equipment and storage medium - Google Patents
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Abstract
The present disclosure provides an operation tracking method of a chip, a board card, an electronic device, and a storage medium, wherein the operation tracking method of the chip includes: in the process of executing each instruction in the target program by the chip, judging whether the jump step length between the first instruction to be executed and the second instruction currently being executed is larger than or equal to a preset step length threshold value; recording address information of a storage unit for storing the first instruction in response to the jump step length being greater than or equal to the step length threshold; and the recorded address information is used for determining the running process of the chip.
Description
Technical Field
The disclosure relates to the technical field of software development, and in particular relates to a chip operation tracking method, a chip, a board card, electronic equipment and a storage medium.
Background
For some micro control units (Micro Controller Unit, MCU) in a System on Chip (SoC) which is independently developed, a problem of program locking is often encountered in software debugging, generally, a joint test working group (Joint Test Action Group, JTAG) may be used to analyze a problem related to program locking, but JTAG generally only can track a problem which is easily reproduced, and is a single-step tracking at a specific location, so that only one final location when the program is locked can be obtained, and a cause of program locking cannot be analyzed.
Disclosure of Invention
The embodiment of the disclosure at least provides a chip operation tracking method, a chip, a board card, electronic equipment and a storage medium.
In a first aspect, an embodiment of the present disclosure provides a method for tracking operation of a chip, including:
In the process of executing each instruction in the target program by the chip, judging whether the jump step length between the first instruction to be executed and the second instruction currently being executed is larger than or equal to a preset step length threshold value;
Recording address information of a storage unit for storing the first instruction in response to the jump step length being greater than or equal to the step length threshold; and the recorded address information is used for determining the running process of the chip.
In an alternative embodiment, the determining whether the jump step size between the first instruction to be executed and the second instruction currently being executed is greater than or equal to a preset step size threshold includes:
receiving a program counter signal sent by a chip controller; the program counter signal carries address information of a storage unit for storing the first instruction;
Determining an address step size between the first instruction and the second instruction based on the address information of the first instruction and the address information of the second instruction which are currently being executed and are carried in the program counter signal;
and taking the address step length as the jump step length, and judging whether the jump step length is larger than or equal to the step length threshold value.
In an alternative embodiment, the program counter signal further carries an instruction type of the first instruction;
Before determining an address step size between the first instruction and the second instruction based on the address information of the first instruction and the address information of the second instruction currently being executed, which are carried in the program counter signal, the method further comprises:
judging whether the first instruction is an instruction of a preset type or not based on the instruction type carried in the program counter signal;
the determining an address step between the first instruction and the second instruction based on the address information of the first instruction and the address information of the second instruction currently being executed carried in the program counter signal includes:
and responding to the first instruction as the instruction of the preset type, and determining an address step length between the first instruction and the second instruction based on the address information of the first instruction and the address information of the second instruction which are currently executed and are carried in the program counter signal.
In an alternative embodiment, before determining whether a jump step size between the first instruction to be executed and the second instruction currently being executed is greater than or equal to a preset step size threshold, the method further includes:
determining whether the current state of the chip reaches a preset trigger condition;
The step length of the jump between the first instruction to be executed and the second instruction currently being executed is greater than or equal to a preset step length threshold value, which comprises the following steps:
and judging whether the jump step length between the first instruction to be executed and the second instruction currently being executed is larger than or equal to a preset step length threshold value or not in response to the current state reaching the preset trigger condition.
In an alternative embodiment, the preset trigger condition includes at least one of: the data stored in the preset position in the memory is modified, the chip is subjected to preset interruption, the address information recorded in the program counter signal reaches a preset value, and the chip is abnormal when executing each instruction.
In an alternative embodiment, the recording the address information of the storage unit for storing the first instruction includes:
Generating a snapshot of address information of a storage unit for storing the first instruction;
and storing the snapshot into a preset storage space.
In an alternative embodiment, the method further comprises:
And stopping the operation tracking process of the chip in response to the chip reaching a preset stopping condition when the target program is executed.
In an alternative embodiment, the preset stopping condition includes: the chip is blocked when the target program is executed, and the method further comprises: and after restarting the chip, acquiring the recorded address information, and determining the running process of the chip based on the acquired address information.
In an alternative embodiment, the method further comprises:
Responding to the recorded address information reaching a preset state, and sending an interrupt signal to a chip controller; the interrupt signal is used for triggering the chip controller to execute processing operation with the interrupt signal.
In a second aspect, embodiments of the present disclosure further provide a chip, including: a chip operation tracking circuit and a memory unit; the chip operation tracking circuit is used for: in the process of executing each instruction in the target program by the chip, judging whether the jump step length between the first instruction to be executed and the second instruction currently being executed is larger than or equal to a preset step length threshold value; and storing address information of a storage unit for storing the first instruction to the storage unit in response to the jump step size being greater than or equal to the step size threshold.
In a third aspect, an embodiment of the present disclosure further provides a board card, including: a package structure in which the chip according to the second aspect is packaged.
In a fourth aspect, an embodiment of the present disclosure further provides an electronic device, including: a processor, a memory and a bus, the memory storing machine-readable instructions executable by the processor, the processor and the memory in communication via the bus when the electronic device is running, the machine-readable instructions when executed by the processor performing the steps of the first aspect, or any of the possible implementations of the first aspect.
In a fifth aspect, the presently disclosed embodiments also provide a computer readable storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of the first aspect, or any of the possible implementations of the first aspect.
According to the operation tracking method of the chip, the board card, the electronic equipment and the storage medium, whether the first instruction to be executed is recorded or not is determined by judging the size relation between the jump step length between every two adjacent instructions in the chip execution target program and the preset step length threshold; when the recording is determined to be needed, the address information of the storage unit for storing the first instruction is recorded, and the address information can be used for reproducing the detailed process of each instruction process in the execution target program of the chip, so that the reason of program blocking can be determined according to the recorded address information when the program is blocked by running.
The foregoing objects, features and advantages of the disclosure will be more readily apparent from the following detailed description of the preferred embodiments taken in conjunction with the accompanying drawings.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for the embodiments are briefly described below, which are incorporated in and constitute a part of the specification, these drawings showing embodiments consistent with the present disclosure and together with the description serve to illustrate the technical solutions of the present disclosure. It is to be understood that the following drawings illustrate only certain embodiments of the present disclosure and are therefore not to be considered limiting of its scope, for the person of ordinary skill in the art may admit to other equally relevant drawings without inventive effort.
FIG. 1 shows a flow chart of a method for tracking operation of a chip provided by an embodiment of the disclosure;
FIG. 2 is a schematic diagram of a chip structure according to an embodiment of the disclosure;
FIG. 3 illustrates a flowchart of another method of operation tracking of a chip provided by an embodiment of the present disclosure;
FIG. 4 shows a schematic diagram of a chip provided by an embodiment of the present disclosure;
FIG. 5 illustrates a schematic diagram of a board provided by an embodiment of the present disclosure;
Fig. 6 shows a schematic diagram of an electronic device provided by an embodiment of the disclosure.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are only some embodiments of the present disclosure, but not all embodiments. The components of the embodiments of the present disclosure, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present disclosure provided in the accompanying drawings is not intended to limit the scope of the disclosure, as claimed, but is merely representative of selected embodiments of the disclosure. All other embodiments, which can be made by those skilled in the art based on the embodiments of this disclosure without making any inventive effort, are intended to be within the scope of this disclosure.
According to research, aiming at a few micro control units in an independently developed system-in-chip, the problem of program locking is often encountered in software debugging, generally, the related problem of program locking can be analyzed by utilizing a combined test working group, but the problem which is easy to reproduce can be generally tracked by the combined test working group, and the single-step tracking is performed at a specific position, so that only one final position when the program is locked can be obtained, and the cause or root cause of the program locking can not be analyzed. When the combined test working group works, the running program can be stopped, and then single-step tracking is carried out to determine the position where the problem exists. However, in some very well defined parts of the problem, the joint test workgroup can start to run in a single step from the previous moment of the problem, and since the even problem is unpredictable, only the deterministic problem can be tracked in a single step. And under the condition that the program blocking problem occurs, only the last blocking problem can be seen through the joint test working group, and the cause of the program blocking can not be tracked. Therefore, it is necessary to design a chip or hardware logic that can record the running process of the chip and analyze the cause of program sticking based on the recorded running process.
In addition, the problem of recurrence of the program jam cause can be solved by using a method of adding points or printing logs. However, the method of recording logs can only ensure that logs are recorded at the positions where the logs are considered to be possibly jammed, and for some occasional problems of program jam, enough recorded logs cannot be ensured to be added to help to analyze the jam problem, so that a certain probability of incomplete log recording at the jam positions exists, and the analysis of the program jam problem is affected because some jam conditions cannot be recorded.
Based on the above study, the present disclosure provides an operation tracking method of a chip, which determines whether to record a first instruction to be executed by judging a size relationship between a jump step length between every two adjacent instructions in a chip execution target program and a preset step length threshold; when the recording is determined to be needed, the address information of the storage unit for storing the first instruction is recorded, and the address information can be used for reproducing the detailed process of each instruction process in the execution target program of the chip, so that the reason of program blocking can be determined according to the recorded address information when the program is blocked by running.
The present invention is directed to a method for manufacturing a semiconductor device, and a semiconductor device manufactured by the method.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
For the sake of understanding the present embodiment, first, a detailed description will be given of a method for tracking operation of a chip disclosed in an embodiment of the present disclosure, where an execution body of the method for tracking operation of a chip provided in an embodiment of the present disclosure is generally an electronic device having a certain computing capability, and the electronic device includes, for example: the terminal device or server or other processing device may be a User Equipment (UE), a mobile device, a User terminal, a terminal, etc. In some possible implementations, the method of tracking the operation of the chip may be implemented by way of a processor invoking computer readable instructions stored in a memory.
The following describes an operation tracking method of a chip provided by the embodiment of the present disclosure, taking an execution body as a terminal device.
Referring to fig. 1, a flowchart of a method for tracking operation of a chip according to an embodiment of the present disclosure is shown, where the method for tracking operation of a chip includes the following steps S101 and S102, where:
Step S101: and in the process of executing each instruction in the target program by the chip, judging whether the jump step length between the first instruction to be executed and the second instruction currently being executed is larger than or equal to a preset step length threshold value.
Referring to fig. 2, a schematic diagram of a chip structure is provided in an embodiment of the disclosure. As shown in fig. 2, the chip includes a micro control unit 21, a Program Counter (PC) 22, an integrated circuit tracker (Application SPECIFIC INTEGRATED Circuit tracer, ASIC TRACER) 23, a memory (MEM) 24, and the like.
Wherein, the micro control unit is also called a single chip Microcomputer (SINGLE CHIP microcomputers, SCM) or a single chip Microcomputer, which properly reduces the frequency and specification of a central processing unit (Central Process Unit, CPU), integrates various integrated circuits on a single chip, and forms a chip-level computer; the instruction counter is used for storing the address of the current instruction to be executed and forming the address of the next instruction. The integrated circuit tracker is a component for calling and tracking, and records various network calling conditions in a calling link in a log manner through unified identity card identifiers (Identity Document, ID) so as to achieve the purpose of perspective network calling; the memory is used for storing or temporarily storing log records and the like.
In the embodiment of the present disclosure, each instruction in the chip execution target program may include any one of program control instructions, for example, a branch instruction (branch includes unconditional branch and conditional branch), a program call instruction, a return instruction, a loop control instruction, and the like.
By way of example, each instruction in the chip execution target program may be an arm instruction, and specifically may include a store instruction (str), a load instruction (ldr), a jump instruction (bl), a return instruction (ret), a loop instruction (loop), and the like.
In one possible implementation, during the execution of the target program by the chip, a jump is required according to a plurality of instructions, and a certain jump step length is corresponding to each two adjacent instructions, but because of the limited storage space of the memory, if each instruction is recorded, only local instruction execution content can be recorded, which is not beneficial to global recording, and for some instructions, such as some loop instructions, the recording may be a PC value inside a loop, so that PC content before the loop cannot be tracked, which may cause the PC content in the loop instruction to be repeatedly recorded, and waste the storage space. Thus, in embodiments of the present disclosure, a step threshold may be preset; determining whether to record the first instruction to be executed by judging whether the jump step length between the first instruction to be executed and the second instruction currently being executed is larger than or equal to a preset step length threshold value. The preset step length threshold value can be determined according to the operation tracking requirement, or a default step length set by the chip is determined as the step length threshold value.
In the disclosed embodiment, as shown in fig. 2, a user (user) may set a parameter condition (paramcondition) as a step size threshold. By way of example, the default step size set by the chip is 100, that is to say that a jump step size between the first instruction and the second instruction currently being executed is equal to or exceeds 100, but if an instruction is desired to record a jump step size between the first instruction and the second instruction currently being executed exceeding 1000, the step size threshold may be set to 1000, that is to say that a jump step size between the first instruction and the second instruction currently being executed exceeding 1000 is recorded.
For example, an appropriate step threshold is set according to the jump step length between a first instruction corresponding to the target program and a second instruction currently being executed, so that too little recorded information caused by too long step threshold is avoided, and important information is omitted; too much recorded information caused by too small step size threshold value is avoided, so that the recorded information is incomplete and the running process can not be traced. The user can set the step threshold according to the actual requirement.
In one possible embodiment, the step S101 "determining whether the jump step size between the first instruction to be executed and the second instruction currently being executed is greater than or equal to the preset step size threshold" may include the following steps S1011 to S1013, wherein:
Step S1011, receiving a program counter signal sent by the chip controller; the program counter signal carries address information of a storage unit for storing the first instruction;
Step S1012, determining an address step size between the first instruction and the second instruction based on the address information of the first instruction and the address information of the second instruction currently being executed carried in the program counter signal;
Step S1013, the address step is used as the jump step, and whether the jump step is larger than or equal to the step threshold is judged.
In the embodiment of the disclosure, the chip controller may be a central processor in the chip, and the central processor may generate corresponding operation control signals according to the received instructions and send the corresponding operation control signals to corresponding components, so as to control the components to act according to the requirements of the instructions.
In another possible embodiment, the chip controller may also be a micro-control unit in one chip, in which the following basic architecture may be included:
(1) A Program memory (Program ROM) which is a read-only and non-writable memory unit in the microcontroller, the memory being used mainly for storing running programs;
(2) Random access Memory (Random Access Memory, RAM), also known as Read/Write Memory (R/WM), is used to temporarily store data, or where program execution stores data;
(3) An Accumulator (Accumulator), which is the operating hub of the micro-control unit, about which 80% of the instructions are associated, and in which some of the data required for the program operation can be stored until the bus or other unit is ready to accept, or until the program is needed;
(4) Registers (registers) are used for temporarily storing data in the micro-control units, and each Register has different functions, but has a common characteristic of being capable of directly reading/writing, so that unnecessary waiting and addressing time is reduced because the registers are positioned in the micro-control units, and input/output (I/O ports) of the micro-control units are also used for directly accessing and controlling in a Register mode;
(5) An arithmetic logic unit (Algorithm Logic Unit, ALU) which functions to execute arithmetic instructions and logic decisions;
(6) I/O expansion is not a goal in single chip microcomputer applications, but rather to provide an input/output channel for external devices as a communication channel between the outside world and the microcontrol unit. Such as keyboard, display, drive switch control or measurement, etc.; peripheral hardware circuit characteristics connected with the I/O expansion must be considered when the I/O expansion is performed, such as: potential matching, interference suppression, and driving capability (e.g., source, sink capability), etc.
In some possible embodiments, the micro-control unit may further include a Timer (Timer), a Counter (EC), a stack and a stack pointer, etc., which are not described herein.
In the embodiment of the disclosure, an integrated circuit tracker, a memory and the like are added in a chip based on a micro control unit so as to fulfill the aim of tracking the operation of the chip.
In the disclosed embodiment, the program counter signal may be sent out by a developed chip and obtained by an ASIC. The program counter signal carries address information of a storage unit for storing the first instruction; this is to ensure that the target program is continuously executing and the chip controller in the chip needs to take some means to determine the address of the next instruction. Before the target program starts to execute, the starting address, i.e. the address of the memory unit where an instruction of the target program is located, needs to be sent to the instruction counter, so that the content of the instruction counter is the address of the first instruction fetched from the memory. When executing an instruction, the chip controller will automatically modify the contents of the instruction counter, i.e. per instruction executed, the instruction counter is incremented by an amount equal to the number of bytes the instruction contains, so that the contents held in the instruction counter always are the address of the next instruction to be executed.
In the disclosed embodiment, the bit width of the PC value in the address information of the first instruction and the address information of the second instruction that is currently being executed is equal to determine an address step size between the two based on the address information of the first instruction and the address information of the second instruction. And then taking the address step length as the jump step length, and judging whether the jump step length is larger than or equal to the step length threshold value based on the address step length.
In the embodiment of the disclosure, the ASIC records the first instruction from the beginning, detects the PC signal sent out by the CPU in the running process and the PC value included in the PC signal all the time, and determines, based on the address step indicated by the PC values corresponding to the two instructions, whether the jump step is greater than or equal to the step threshold.
In a possible implementation manner, the program counter signal also carries an instruction type of the first instruction. Correspondingly, before step S1012 "determining an address step size between the first instruction and the second instruction based on the address information of the first instruction and the address information of the second instruction currently being executed carried in the program counter signal", the following is further included:
judging whether the first instruction is an instruction of a preset type or not based on the instruction type carried in the program counter signal;
Step S1012 "determining an address step size between the first instruction and the second instruction based on the address information of the first instruction and the address information of the second instruction currently being executed carried in the program counter signal" includes:
and responding to the first instruction as the instruction of the preset type, and determining an address step length between the first instruction and the second instruction based on the address information of the first instruction and the address information of the second instruction which are currently executed and are carried in the program counter signal.
The instruction type of the first instruction is an operation code of a PC value in a PC signal corresponding to the first instruction, whether the first instruction is an instruction of a preset type can be judged based on the operation code, the operation code comprises address information corresponding to the first instruction, and the address step length between the two instructions can be determined by analyzing the operation codes of the two instructions.
For example, in an embodiment of the present disclosure, the instruction of the preset type may be a jump instruction, and after determining that the first instruction is a jump instruction, the address step between the first instruction and the second instruction may be determined based on address information of the first instruction carried by an operation code in a program counter signal and address information of a second instruction that is currently being executed.
In another possible embodiment, before determining in step S101 "whether the jump step size between the first instruction to be executed and the second instruction currently being executed is greater than or equal to the preset step size threshold", the following is further included:
determining whether the current state of the chip reaches a preset trigger condition;
Step S101 "determining whether the jump step size between the first instruction to be executed and the second instruction currently being executed is greater than or equal to the preset step size threshold" includes the following:
and judging whether the jump step length between the first instruction to be executed and the second instruction currently being executed is larger than or equal to a preset step length threshold value or not in response to the current state reaching the preset trigger condition.
Wherein the preset trigger condition includes one or more of the following: the data stored in the preset position in the memory is modified, the chip is subjected to preset interruption, the address information recorded in the program counter signal reaches a preset value, and the chip is abnormal when executing each instruction.
For example, some initial conditions may be input as trigger conditions to start triggering the recording of the first instruction, for example, the memory of a specific location is modified (including the file or data stored in the specific location is changed, etc.), the running of the target program is interrupted or abnormal (including the situation that the target program is jammed, locked, etc.), some recording positions in the program counter signal reach a certain value (including the recording stored in the program counter signal reaches the upper storage limit of the program counter or exceeds a certain proportion threshold value), etc.
Step S102: recording address information of a storage unit for storing the first instruction in response to the jump step length being greater than or equal to the step length threshold; and the recorded address information is used for determining the running process of the chip.
Wherein address information of the first instruction may be stored in a register and the running process of the chip may be determined based on the address information.
Specifically, the recording of address information of a storage unit for storing the first instruction includes the following:
generating a snapshot of address information of a storage unit for storing the first instruction, and storing the snapshot into a preset storage space.
In the embodiment of the disclosure, when the target program is restarted, a snapshot of the address information of the storage unit of the first instruction is saved, so that when the target program is restarted after being blocked, the address information of the storage unit of the first instruction can be derived and analyzed. Therefore, the running process of the MCU can be tracked by deriving the recorded address information, and the cause of the blocking of the target program can be found.
For example, after the target program is restarted, the target program returns to the initial state, where no part of the program is blocked, but the chip may determine that the restart cause is due to the program blocking, because before the target program is restarted, the restart cause is recorded in the storage space, for example, a value in the register is changed to a specific value, such as 0x55aa55aa, so that when the target program is operated to the specific value, it is known that the last time the program is restarted due to the program blocking, and a file backup (dump) function is triggered, so that the up-and-down operation record of the blocking position in the history record of the target program is derived. As shown in fig. 2, a file backup may be triggered from memory to derive a running record.
In another possible embodiment, the operation tracking method of the chip further includes:
And stopping the operation tracking process of the chip in response to the chip reaching a preset stopping condition when the target program is executed.
Wherein the preset stopping condition includes: the chip is blocked when the target program is executed, and the method further comprises: and after restarting the chip, acquiring the recorded address information, and determining the running process of the chip based on the acquired address information.
For example, the recorded address information includes the address information of the first instruction and the address information of the second instruction, and some stop conditions may be input as trigger conditions to start to terminate the recording of the first instruction, for example, the memory of a specific location is modified, the running of the target program is interrupted or abnormal, some recording positions in the program counter signal reach a certain value, etc.
In another possible embodiment, the operation tracking method of the chip further includes:
Responding to the recorded address information reaching a preset state, and sending an interrupt signal to a chip controller; the interrupt signal is used for triggering the chip controller to execute processing operation with the interrupt signal.
In some possible embodiments, after recording address information of a storage unit for storing the first instruction, the method may further include:
determining at least one running process record composed of address information; each running process record comprises address information corresponding to a plurality of first instructions. And responding to the blocking of the target program, determining abnormal address information corresponding to the abnormal first instruction with the blocking, and tracing the record of the abnormal operation process where the abnormal address information is located.
Wherein, based on the plurality of first instructions, determining at least one running process record constituted by the first instructions may include:
Determining calling relations among a plurality of first instructions, and constructing at least one running process record comprising address information of the first instructions based on the calling relations among the plurality of first instructions; the running process record comprises address information corresponding to a plurality of first instructions and calling relations among the plurality of first instructions.
In the embodiment, in response to the target program being jammed, the running information of the target program in the running process is saved and imported into a storage folder; the running information can be exported when the target program runs again; the operation information comprises a plurality of the first instructions and at least one operation process record formed by the first instructions.
In the embodiment of the disclosure, a trigger condition may be set, when ASIC TRACER finds the trigger condition, an interrupt is reported to the running process, at this time, the CPU interrupts the target program, and makes a behavior analysis, such as printing a stack, according to the interrupt process.
For example, several cases may be included to trigger the interrupt signal, and a trigger address may be set in the ASIC, and the trigger condition of the trigger (trigger) may be set as follows: if the PC value is the trigger address, triggering interruption and sending an interruption signal, so that the CPU can control the ASIC to stop recording the running process of the target program after receiving the interruption signal, and derive the historical PC record stored in the storage position, thereby obtaining the running process of the target program; or, a range of PC values, for example, 0X10000 to 0X10200, may be set in two registers of the ASIC, and then when the PC executes within the range of PC values, the trigger triggers an interrupt, and at this time, the running process of the PC before the interval may be invoked, so that the cause of triggering the interrupt and the corresponding instruction position are located.
In an exemplary embodiment, in response to the target program being jammed, determining an abnormal first instruction in the target program that is jammed, determining a running process record in which the abnormal first instruction is located based on at least one running process record stored in the storage folder, and determining the running process record in which the abnormal first instruction is located as an abnormal running process record. Therefore, the cause of the blocking of the target program or the abnormal instruction causing the blocking can be determined based on the abnormal operation process record, and the subsequent repair work based on the abnormal instruction is facilitated.
Referring to fig. 3, a flowchart of another method for tracking operation of a chip according to an embodiment of the present disclosure is shown, where the method for tracking operation of a chip includes the following steps S301 to S307:
Step S301: setting parameter conditions;
Step S302: recording is started;
Step S303: whether to start recording; if yes, go to step S304, if no, go to step S302;
Step S304: recording address information of a first instruction;
step S305: whether to stop recording; if yes, go to step S306, if no, go to step S304;
step S306: stopping recording;
step S307: and (5) backing up the record.
In the embodiment of the disclosure, in response to starting running of a target program, setting a parameter condition as a preset step threshold, and based on the condition that the starting recording is triggered, judging whether a jump step length between a first instruction to be executed and a second instruction currently being executed is larger than or equal to the preset step threshold, if so, recording address information of the first instruction, and if not, restarting recording; and responding to whether a recording stopping condition is triggered, stopping recording and backing up recording if yes, and continuing recording if no.
According to the embodiment of the disclosure, whether the first instruction to be executed is recorded is determined by judging the size relation between the jump step length between every two adjacent instructions in the chip execution target program and the preset step length threshold; when the recording is determined to be needed, the address information of the storage unit for storing the first instruction is recorded, and the address information can be used for reproducing the detailed process of the chip in the process of executing each instruction in the target program, so that the reason of program blocking can be determined according to the recorded address information when the program is blocked by running, and the detailed running condition of the program before the program is blocked by running can be reproduced.
It will be appreciated by those skilled in the art that in the above-described method of the specific embodiments, the written order of steps is not meant to imply a strict order of execution but rather should be construed according to the function and possibly inherent logic of the steps.
Based on the same inventive concept, the embodiments of the present disclosure further provide a chip corresponding to the operation tracking method of the chip, and since the principle of solving the problem by the chip in the embodiments of the present disclosure is similar to that of the operation tracking method of the chip in the embodiments of the present disclosure, the implementation of the chip may refer to the implementation of the method, and the repetition is omitted.
Referring to fig. 4, which is a schematic diagram of a chip provided in an embodiment of the disclosure, the chip 400 includes: chip operation tracking circuit 410, and memory cell 420;
The chip operation tracking circuit 410 is configured to: in the process of executing each instruction in the target program by the chip, judging whether the jump step length between the first instruction to be executed and the second instruction currently being executed is larger than or equal to a preset step length threshold value; in response to the jump step size being greater than or equal to the step size threshold, address information of a memory location 420 for storing the first instruction is stored to the memory location 420.
In an alternative embodiment, the chip running tracking circuit 410 is configured to, when determining whether a jump step size between a first instruction to be executed and a second instruction currently being executed is greater than or equal to a preset step size threshold:
receiving a program counter signal sent by a chip controller; wherein the program counter signal carries address information of a storage unit 420 storing the first instruction;
Determining an address step size between the first instruction and the second instruction based on the address information of the first instruction and the address information of the second instruction which are currently being executed and are carried in the program counter signal;
And taking the address step length as the jump step length, and judging whether the jump step length is larger than or equal to the step length threshold value.
In an alternative embodiment, the program counter signal further carries an instruction type of the first instruction;
The chip operation tracking circuit 410 is further configured to, before determining an address step size between the first instruction and the second instruction based on address information of the first instruction carried in the program counter signal and address information of the second instruction currently being executed:
judging whether the first instruction is an instruction of a preset type or not based on the instruction type carried in the program counter signal;
The chip operation tracking circuit 410 is configured to, when determining an address step between the first instruction and the second instruction based on the address information of the first instruction and the address information of the second instruction currently being executed, determine, in response to the first instruction being the instruction of the preset type, an address step between the first instruction and the second instruction based on the address information of the first instruction and the address information of the second instruction currently being executed, which are carried in the program counter signal.
In an alternative embodiment, the chip running tracking circuit 410 is further configured, before determining whether a jump step size between the first instruction to be executed and the second instruction currently being executed is greater than or equal to a preset step size threshold, to:
determining whether the current state of the chip reaches a preset trigger condition;
the chip operation tracking circuit 410 is configured to, when determining whether a jump step size between a first instruction to be executed and a second instruction currently being executed is greater than or equal to a preset step size threshold value:
and judging whether the jump step length between the first instruction to be executed and the second instruction currently being executed is larger than or equal to a preset step length threshold value or not in response to the current state reaching the preset trigger condition.
In an alternative embodiment, the preset trigger condition includes at least one of: the data stored in the preset position in the memory is modified, the chip is subjected to preset interruption, the address information recorded in the program counter signal reaches a preset value, and the chip is abnormal when executing each instruction.
In an alternative embodiment, the chip running trace circuit 410 is configured to, when recording address information of the memory unit 420 for storing the first instruction:
generating a snapshot of address information of a storage unit 420 for storing the first instruction;
and storing the snapshot into a preset storage space.
In an alternative embodiment, the chip operation tracking circuit 410 is further configured to:
And stopping the operation tracking process of the chip in response to the chip reaching a preset stopping condition when the target program is executed.
In an alternative embodiment, the preset stopping condition includes: the chip is locked when executing the target program, and the storage unit 420 is further configured to: and after restarting the chip, acquiring the recorded address information, and determining the running process of the chip based on the acquired address information.
In an alternative embodiment, the chip operation tracking circuit 410 is further configured to:
Responding to the recorded address information reaching a preset state, and sending an interrupt signal to a chip controller; the interrupt signal is used for triggering the chip controller to execute processing operation with the interrupt signal.
According to the embodiment of the disclosure, whether the first instruction to be executed is recorded is determined by judging the size relation between the jump step length between every two adjacent instructions in the chip execution target program and a preset step length threshold; when the recording is determined to be needed, the address information of the storage unit for storing the first instruction is recorded, and the address information can be used for reproducing the detailed process of each instruction process in the execution target program of the chip, so that the reason of program blocking can be determined according to the recorded address information when the program is blocked by running.
The description of the processing flow of each part in the chip and the interaction flow between each part can refer to the related description in the method embodiment, and will not be described in detail here.
Based on the same technical concept, the embodiment of the disclosure also provides a board card, which comprises a packaging structure packaged with at least one chip. Referring to fig. 5, an exemplary board card 500 is provided, which includes the chip and may further include other components, including but not limited to: a memory device 501 and an interface means 504.
The memory device is connected with the chip in the chip packaging structure through a bus and is used for storing data. The memory device 501 may include multiple sets of memory cells 502, for example: double speed synchronous dynamic random access memory (Double DATA RATE SDRAM, DDR SDRAM), and the like. Each set of memory cells 502 is connected to the chip 503 via a bus.
The interface device 504 is electrically connected to a chip within the chip 503 package structure. The interface device 504 is used to implement data transmission between the chip 503 and an external device 505 (e.g., a terminal, a server, a camera, etc.). In one embodiment, the interface device may include a high-speed serial computer expansion bus standard (PERIPHERAL COMPONENT INTERCONNECT EXPRESS, PCIE) interface, a network interface, or other interfaces, which is not limited by the present disclosure.
The embodiments of the present disclosure also provide an electronic device, including a data processing device as described in any of the embodiments of the present disclosure, or a chip as described in the embodiments of the present disclosure. Referring to fig. 6, a schematic structural diagram of an electronic device according to an embodiment of the disclosure includes a processor 601, a memory 602, and a bus 603. The memory 602 is used for storing execution instructions, including a memory 6021 and an external memory 6022; the memory 6021 is also referred to as an internal memory, and is used for temporarily storing operation data in the processor 601 and data exchanged with the external memory 6022 such as a hard disk, the processor 601 exchanges data with the external memory 6022 through the memory 6021, and when the electronic device is running, the processor 601 and the memory 602 communicate through the bus 603, so that the processor 601 executes the following instructions:
In the process of executing each instruction in the target program by the chip, judging whether the jump step length between the first instruction to be executed and the second instruction currently being executed is larger than or equal to a preset step length threshold value;
Recording address information of a storage unit for storing the first instruction in response to the jump step length being greater than or equal to the step length threshold; and the recorded address information is used for determining the running process of the chip.
The disclosed embodiments also provide a computer readable storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of the method of tracking the operation of a chip described in the above method embodiments. Wherein the storage medium may be a volatile or nonvolatile computer readable storage medium.
The computer program product of the method for tracking the operation of the chip provided in the embodiments of the present disclosure includes a computer readable storage medium storing program codes, where the instructions included in the program codes may be used to execute the steps of the method for tracking the operation of the chip described in the embodiments of the method, and the embodiments of the method may be referred to specifically, and are not described herein.
The disclosed embodiments also provide a computer program which, when executed by a processor, implements any of the methods of the previous embodiments. The computer program product may be realized in particular by means of hardware, software or a combination thereof. In an alternative embodiment, the computer program product is embodied as a computer storage medium, and in another alternative embodiment, the computer program product is embodied as a software product, such as a software development kit (Software Development Kit, SDK), or the like.
It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described system and apparatus may refer to corresponding procedures in the foregoing method embodiments, which are not described herein again. In the several embodiments provided in the present disclosure, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. The above-described apparatus embodiments are merely illustrative, for example, the division of the units is merely a logical function division, and there may be other manners of division in actual implementation, and for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some communication interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in each embodiment of the present disclosure may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a non-volatile computer readable storage medium executable by a processor. Based on such understanding, the technical solution of the present disclosure may be embodied in essence or a part contributing to the prior art or a part of the technical solution, or in the form of a software product stored in a storage medium, including several instructions for causing an electronic device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in the embodiments of the present disclosure. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
Finally, it should be noted that: the foregoing examples are merely specific embodiments of the present disclosure, and are not intended to limit the scope of the disclosure, but the present disclosure is not limited thereto, and those skilled in the art will appreciate that while the foregoing examples are described in detail, it is not limited to the disclosure: any person skilled in the art, within the technical scope of the disclosure of the present disclosure, may modify or easily conceive changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features thereof; such modifications, changes or substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the disclosure, and are intended to be included within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (13)
1. A method for tracking operation of a chip, comprising:
In the process of executing each instruction in the target program by the chip, judging whether the jump step length between the first instruction to be executed and the second instruction currently being executed is larger than or equal to a preset step length threshold value;
Recording address information of a storage unit for storing the first instruction in response to the jump step length being greater than or equal to the step length threshold; and the recorded address information is used for determining the running process of the chip.
2. The method of claim 1, wherein determining whether a jump step size between a first instruction to be executed and a second instruction currently being executed is greater than or equal to a preset step size threshold comprises:
receiving a program counter signal sent by a chip controller; the program counter signal carries address information of a storage unit for storing the first instruction;
Determining an address step size between the first instruction and the second instruction based on the address information of the first instruction and the address information of the second instruction which are currently being executed and are carried in the program counter signal;
and taking the address step length as the jump step length, and judging whether the jump step length is larger than or equal to the step length threshold value.
3. The method of claim 2, wherein the program counter signal also carries an instruction type of the first instruction;
Before determining an address step size between the first instruction and the second instruction based on the address information of the first instruction and the address information of the second instruction currently being executed, which are carried in the program counter signal, the method further comprises:
judging whether the first instruction is an instruction of a preset type or not based on the instruction type carried in the program counter signal;
the determining an address step between the first instruction and the second instruction based on the address information of the first instruction and the address information of the second instruction currently being executed carried in the program counter signal includes:
and responding to the first instruction as the instruction of the preset type, and determining an address step length between the first instruction and the second instruction based on the address information of the first instruction and the address information of the second instruction which are currently executed and are carried in the program counter signal.
4. A method according to any of claims 1-3, further comprising, prior to determining whether a jump step size between a first instruction to be executed and a second instruction currently being executed is greater than or equal to a preset step size threshold:
determining whether the current state of the chip reaches a preset trigger condition;
The step length of the jump between the first instruction to be executed and the second instruction currently being executed is greater than or equal to a preset step length threshold value, which comprises the following steps:
and judging whether the jump step length between the first instruction to be executed and the second instruction currently being executed is larger than or equal to a preset step length threshold value or not in response to the current state reaching the preset trigger condition.
5. The method of claim 4, wherein the preset trigger condition comprises at least one of: the data stored in the preset position in the memory is modified, the chip is subjected to preset interruption, the address information recorded in the program counter signal reaches a preset value, and the chip is abnormal when executing each instruction.
6. The method of any of claims 1-5, wherein the recording address information of a memory location for storing the first instruction comprises:
Generating a snapshot of address information of a storage unit for storing the first instruction;
and storing the snapshot into a preset storage space.
7. The method according to any one of claims 1-6, further comprising:
And stopping the operation tracking process of the chip in response to the chip reaching a preset stopping condition when the target program is executed.
8. The method of claim 7, wherein the preset stop condition comprises: the chip is blocked when the target program is executed;
The method further comprises the steps of:
and after restarting the chip, acquiring the recorded address information, and determining the running process of the chip based on the acquired address information.
9. The method according to any one of claims 1-8, further comprising:
Responding to the recorded address information reaching a preset state, and sending an interrupt signal to a chip controller; the interrupt signal is used for triggering the chip controller to execute processing operation with the interrupt signal.
10. A chip, comprising: a chip operation tracking circuit and a memory unit; the chip operation tracking circuit is used for: in the process of executing each instruction in the target program by the chip, judging whether the jump step length between the first instruction to be executed and the second instruction currently being executed is larger than or equal to a preset step length threshold value; and storing address information of a storage unit for storing the first instruction to the storage unit in response to the jump step size being greater than or equal to the step size threshold.
11. A board card, comprising: a package structure in which the chip according to claim 10 is packaged.
12. An electronic device, comprising: a chip as claimed in claim 10, or comprising a board as claimed in claim 11.
13. A computer-readable storage medium, on which a computer program is stored, which computer program, when being executed by a processor, performs the steps of the method of operation tracking of a chip as claimed in any of claims 1-9.
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| CN202410257331.7A CN118132427A (en) | 2024-03-06 | 2024-03-06 | Chip operation tracking method, chip, board card, electronic equipment and storage medium |
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