CN115576734A - Multi-core heterogeneous log storage method and system - Google Patents

Multi-core heterogeneous log storage method and system Download PDF

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Publication number
CN115576734A
CN115576734A CN202211443012.2A CN202211443012A CN115576734A CN 115576734 A CN115576734 A CN 115576734A CN 202211443012 A CN202211443012 A CN 202211443012A CN 115576734 A CN115576734 A CN 115576734A
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memory
core heterogeneous
core
processor
processor cores
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CN115576734B (en
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陈星宇
陈庆
冯坤
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Nanjing Semidrive Technology Co Ltd
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Nanjing Semidrive Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0766—Error or fault reporting or storing
    • G06F11/0787—Storage of error reports, e.g. persistent data storage, storage using memory protection
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
    • G06F11/0724—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU] in a multiprocessor or a multi-core unit
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A multi-core heterogeneous log storage method comprises the following steps: in a multi-core heterogeneous system comprising at least two processor cores with different architectures, storing logs of operating systems in the processor cores into a memory in real time; monitoring the working state of each processor core, and switching to an emergency operating system when one or more processor cores are abnormal; resetting other processor cores which are not abnormal in the multi-core heterogeneous system, and transferring the log stored in the memory to a memory; the emergency operating system and the memory work in a safety function domain. According to the multi-core heterogeneous system log storage method, logs of all processor core operating systems are written into the reserved memory in real time, when the system is abnormal, the emergency operating system is switched to, other processors in the multi-core heterogeneous system are reset, and log data of each processor core stored in the memory are transferred to the storage, so that logs in normal/abnormal states of different processor cores are reliably stored.

Description

Multi-core heterogeneous log storage method and system
Technical Field
The present application relates to the field of data processing technologies, and in particular, to a method and a system for storing a multi-core heterogeneous log.
Background
More and more processor cores are integrated into a System on chip (SoC) and operate independently, so that the SoC integration level is higher and the SoC is more and more complex. At present, logs of a large-core system (Eg: android/Linux) are mainly stored in most multi-core heterogeneous SoCs, logs of other small-core (Eg: MCU, DSP) systems are rarely stored, but for complex heterogeneous systems, although phenomena are directly reflected on the large-core system, problems can be caused by abnormal small-core systems. In some embedded systems, the log is saved immediately after an anomaly is detected, regardless of whether the current log storage process is reliable. Therefore, how to effectively and reliably store the logs in the normal/abnormal states of different processor cores makes it increasingly difficult to effectively analyze the complex stability problem.
Disclosure of Invention
In order to solve the defects in the prior art, the application aims to provide a multi-core heterogeneous log storage method and system, which can reliably store logs in normal/abnormal states of different processor cores and provide the logs for a user to read and analyze after the system is restarted.
In order to achieve the above object, the present application provides a multi-core heterogeneous log storage method, including the following steps:
in a multi-core heterogeneous system comprising at least two processor cores with different architectures, storing logs of operating systems in the processor cores into a memory in real time;
monitoring the working state of each processor core, and switching to an emergency operation system when one or more processor cores are abnormal;
resetting other processor cores which do not have exception in the multi-core heterogeneous system, and transferring the logs stored in the memory to a memory;
the emergency operating system and the memory work in a safety function domain.
Further, still include: the system is initialized, a memory is divided into a plurality of spaces, different spaces and different processor cores are configured to be in the same hardware domain, and the spaces and the processor cores are used for storing log data of the processor cores of the multi-core heterogeneous system.
Further, still include: calling a configuration interface of an operating system to perform write operation; and the configuration interface calls the buffer interface to write the log data into the corresponding memory space.
Further, the method also comprises the following steps: after the log is transferred and stored, the watchdog circuit is triggered to restart the multi-core heterogeneous system, and after the multi-core heterogeneous system is abnormal, the watchdog circuit is triggered to enable the output end of the watchdog circuit to send a reset signal to the multi-core heterogeneous system, so that the system is restarted.
Further, the step of switching to the emergency operation system includes: and calling a system switching function in the exception handling function to switch to the emergency operation system, wherein the exception handling function corresponds to an exception vector table of the system.
The present application further provides a multi-core heterogeneous log storage system, including:
the system anomaly detection module is connected with all processor cores in the multi-core heterogeneous system and used for detecting the running state of each processor core and sending a request signal to the emergency operation system when anomaly is detected;
the emergency operating system receives the request signal, starts and resets other processor cores which are not abnormal in the multi-core heterogeneous system, and transfers the log data stored in the memory to the memory;
and the memory is used for storing the log data when the multi-core heterogeneous system is abnormal.
Further, the system anomaly detection module, the emergency operation system and the memory operate in a functional safety domain.
The application also provides a multi-core heterogeneous log storage chip which comprises the multi-core heterogeneous log storage system.
The application also provides an electronic device, which includes a processor, a memory, and a computer program stored in the memory and executable on the processor, where the processor is configured to execute the computer program stored in the memory, and implement the multi-core heterogeneous log storage method as described above.
The present application also provides a storage medium, where at least one instruction is stored, where the instruction is loaded and executed by a processor to implement the multi-core heterogeneous log storage method described above.
By the multi-core heterogeneous log storage method, the multi-core heterogeneous log storage system, the multi-core heterogeneous log storage chip, the multi-core heterogeneous log storage device and the multi-core heterogeneous log storage medium, log data of a plurality of processor core operating systems are written into a reserved memory in real time, when one or more processor cores are abnormal, an emergency operating system is switched to, other processors in the multi-core heterogeneous system are reset, and then the log data of each processor core stored in the memory are transferred to a storage in a security domain, so that the log information can be reliably stored when the multi-core heterogeneous system is abnormal.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the application.
Drawings
The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application and not limit the application. In the drawings:
FIG. 1 is a flowchart of a multi-core heterogeneous system log storage method according to an embodiment of the present application;
FIG. 2 is a flowchart illustrating a method for storing a log of a multi-core heterogeneous system according to another embodiment of the present disclosure;
FIG. 3 is a schematic diagram of a multi-core heterogeneous log storage system according to the present application;
fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
Embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided for a more thorough and complete understanding of the present application. It should be understood that the drawings and embodiments of the present application are for illustration purposes only and are not intended to limit the scope of the present application.
It should be understood that the various steps described in the method embodiments of the present application may be performed in a different order and/or in parallel. Moreover, method embodiments may include additional steps and/or omit performing the illustrated steps. The scope of the present application is not limited in this respect.
The term "including" and variations thereof as used herein is intended to be open-ended, i.e., "including but not limited to". The term "based on" is "based, at least in part, on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Relevant definitions for other terms will be given in the following description.
It should be noted that the terms "first", "second", etc. may be mentioned in the present application only for distinguishing different devices, modules or units, and are not used for limiting the order or interdependence of the functions performed by these devices, modules or units.
It is noted that references to "a", "an", and "the" modifications in this application are intended to be illustrative rather than limiting, and that those skilled in the art will recognize that reference to "one or more" unless the context clearly dictates otherwise. "plurality" is to be understood as two or more.
Hereinafter, embodiments of the present application will be described in detail with reference to the accompanying drawings.
Example 1
In the embodiment of the application, a log storage method of a multi-core heterogeneous system is provided, wherein in the multi-core heterogeneous system, logs of an operating system in a plurality of processor cores are stored in a memory in real time; and meanwhile, monitoring the working state of each processor core, switching to an emergency operating system when one or more processor cores are abnormal, resetting other processor cores which are not abnormal in the multi-core heterogeneous system, and then transferring the log stored in the memory to the memory.
The multi-core heterogeneous system comprises at least two processor cores with different architectures, wherein hardware resources connected with the processor cores respectively form a plurality of hardware domains which are isolated from each other on hardware.
It is understood that multi-core heterogeneity is a difference at the hardware level, not a difference in operating systems. There may be multiple hardware domains within a multi-core heterogeneous SOC, a hardware domain being a set of resources. Because the processor cores and the processor cores are in heterogeneous arrangement, cache consistency hardware is not arranged between the processor cores and the hardware domains formed by the interrupt controller, the clock controller and the memory of each processor core are in hard isolation, each processor core cannot be directly and uniformly scheduled by an operating system, and hardware resources in the hardware domain of each processor core can only be accessed by the processor core.
Fig. 1 is a flowchart of a multi-core heterogeneous system log storage method according to an embodiment of the present application, and the multi-core heterogeneous system log storage method of the present application will be described in detail with reference to fig. 1.
In step 101, in a multi-core heterogeneous system including at least two processor cores with different architectures, logs of operating systems in the plurality of processor cores are stored in a memory in real time.
In the embodiment of the application, when the system is initialized, the memory of the multi-core heterogeneous system is divided into a plurality of spaces, and different spaces and different processor cores are configured to be in the same hardware domain and used for storing log data of the processor cores in the multi-core heterogeneous system.
In some embodiments, the memory may be a Double Data Rate (DDR) memory, and compared with a conventional single Data Rate, the DDR memory implements two read/write operations within one clock cycle, that is, one read/write operation is performed on a rising edge and a falling edge of a clock respectively.
In step 102, the operating status of each processor core is monitored, and when one or more processor cores are abnormal, the emergency operating system is switched to.
The exception of the processor core referred to in the embodiments of the present application refers to an exception mode in which the operating system is in an exception state, including a prefetch instruction abort exception, an undefined instruction exception, and a data abort access exception, wherein,
the prefetch instruction abort exception occurs at the CPU pipeline fetch stage, and the exception is entered if the target instruction address is an illegal address;
undefined instruction exceptions occur at the decode stage in the pipeline technique, and if the current instruction cannot be identified as a valid instruction, an undefined instruction exception is generated;
a data abort access exception occurs when the address to access the data does not exist or is an illegal address.
In the embodiment of the application, when the CPU detects the abnormality, the system jumps to a proper abnormality vector table according to the type of the abnormality; and a jump function for exception processing is stored in the exception vector table, and the corresponding exception processing function is jumped to for exception processing. When the operation of jumping into the abnormal vector table is abnormal, the hardware automatically completes the operation. For example, taking an ARM architecture as an example, an exception vector table of the ARM architecture is a specific memory address space, each processor exception corresponds to a word length space (4 Bytes), which is exactly a 32-bit instruction length, when an exception occurs, a CPU forcibly sets a value of a PC to be a fixed memory address corresponding to the current exception, and may perform exception handling by writing a jump instruction to the address and jumping to an entry of a predefined exception handler.
In the embodiment of the application, when the multi-core heterogeneous system detects that one or more processor cores are abnormal, the multi-core heterogeneous system automatically jumps to an abnormal processing function corresponding to the abnormal vector table, calls an operating system switching function in the abnormal processing function, and switches to an emergency operating system.
In step 103, other processor cores in the multi-core heterogeneous system, which are not abnormal, are reset, and the log stored in the memory is transferred to a memory.
In the multi-core heterogeneous system, because the possibility that a plurality of processor cores access the same Storage exists, in order to ensure the reliability of writing, other processor cores which are not abnormal are reset actively before the logs are transferred, and then the logs stored in the memory in real time are transferred to the Storage.
In the embodiment of the application, the emergency operating system and the memory for storing the log in the abnormal state should work in the functional safety domain. The function security domain is a combination of independent function entities which meet the high function security level in the complex SOC. Functional safety, which is the derivation of functional safety requirements from safety targets and the assignment of functional safety requirements to preliminary architectural elements or external measures of an item, includes safety measures and safety architecture (see the road vehicle functional safety ISO 26262 standard for details). The functional security domain can process tasks related to functional security and is not affected by hardware outside the functional security domain on the SOC.
The log storage method of the multi-core heterogeneous system can be used for storing log data in a normal/abnormal state of a complex system chip (SOC), can effectively and reliably store the log data even when the system is abnormal, and is used for a user to read and analyze the log data after the system is restarted.
Example 2
Fig. 2 is a flowchart of a method for storing a log of a multi-core heterogeneous system according to another embodiment of the present application, and the workflow of the multi-core heterogeneous system log storage of the present application will be described in detail with reference to fig. 2.
In step 201, after the multi-core heterogeneous system is powered on, a system initialization state is entered.
In step 202, a section of continuous DDR memory area is partitioned from the system memory as a reserved memory, and a section of memory is allocated to each processor core, and the log data of each processor system is stored in real time.
In the embodiment of the application, the DDR memory space configured for each processor core and the processor core thereof are in the same hardware domain.
In step 203, whether the multi-core heterogeneous system is started or abnormally operated is detected.
In the embodiment of the present application, the start-up exception mainly includes an exception that can be detected by the CPU, such as an undefined instruction exception, a prefetch abort exception, a data abort exception, and the like.
And monitoring the working state of the multi-core heterogeneous system in real time, and switching to an emergency operation system in an exception handling function if one or more processor cores are detected to be abnormally started. If the system is normally started, the running state of the multi-core heterogeneous system is continuously monitored; if one or more processor operating systems are detected to be abnormally operated, the emergency operating system is switched to.
In step 204, the system is switched to the emergency operating system, and other processor cores in the heterogeneous system, which are not abnormal, are reset.
In the embodiment of the application, in order to avoid that a plurality of processor cores access the same Storage, and ensure the reliability of writing, before the log unloading operation is performed, other processor cores in the heterogeneous system, which are not abnormal, should be reset, and then the unloading operation of log data is performed, so that the reliability of the log unloading process can be ensured.
In step 205, the system logs of each processor core saved in the DDR memory are transferred to Storage.
In step 206, it is determined whether the log is completely transferred. If the log data is completely stored, triggering a WDT (Watchdog timer) to restart the system; otherwise, the log data is continuously transferred.
In step 207, after the log is transferred, the watchdog circuit is triggered to restart the system.
The watchdog is divided into a hardware watchdog and a software watchdog, and the basic function is to restart the system under the condition of software problems or program runaway. The hardware watchdog mainly utilizes a timer circuit, the timing output of the hardware watchdog is connected to the reset end of the circuit, and a program clears the timer within a certain time range, namely 'feeding the dog', so that the timer can not overflow all the time when the program works normally, and a reset signal can not be generated. If the program fails, the watchdog timer overflows and generates a reset signal and restarts the system without resetting the watchdog within a timing period. The software watchdog is in principle the same, and only the timer on the hardware circuit is replaced by the internal timer of the processor, so that the hardware circuit design can be simplified, but the software watchdog is inferior to the hardware timer in terms of reliability, for example, the internal timer of the system is not capable of detecting the failure.
In the embodiment of the application, monitoring of the log data unloading process is added, complete log information is guaranteed to be stored in the abnormal state of the multi-core heterogeneous system, and then the system is restarted.
Example 3
Fig. 3 is a schematic structural diagram of a multi-core heterogeneous log Storage system according to the present application, and as shown in fig. 3, the multi-core heterogeneous log Storage system of the present application includes a plurality of operating systems 10, a system abnormality detection module 20, an Emergency OS (Emergency operating system) 30, and a Storage (Storage) 40, wherein,
the log of each operating system 10 is written into the corresponding DDR buffer in real time in a normal state. In the process of storing the log in real time, a console interface (configuration interface) of an operating system is called for writing first, and then the console interface calls a buffer interface to write the log into a corresponding DDR buffer.
The system anomaly detection module 20 detects the state of each operating system 10, and sends a request signal to the emergency operating system 30 when one or more processor cores are detected to be anomalous.
The emergency operating system 30, after resetting other processor cores of the operating system 10, transfers all logs stored in the DDR buffer to the memory (Storage) 40, and after the system is restarted, provides the user with reading and analysis.
In the embodiment of the present application, the system anomaly detection module 20, the emergency operating system 30, and the Storage40 operate in the functional security domain, so that the accuracy and reliability of system anomaly detection are improved.
Example 4
In an embodiment of the present application, a multi-core heterogeneous chip is further provided, including the multi-core heterogeneous log storage system described above.
Example 5
In an embodiment of the present application, there is also provided an electronic device, and fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present application, as shown in fig. 4, the electronic device of the present application includes a processor 401 and a memory 402, wherein,
the memory 402 stores a computer program which, when read and executed by the processor 401, performs the steps in the multi-core heterogeneous system log storage method embodiment as described above.
Example 6
In an embodiment of the present application, a computer-readable storage medium is further provided, where the computer program is configured to, when executed, perform the steps in the multi-core heterogeneous system log storage method embodiment as described above.
In this embodiment, the computer-readable storage medium may include, but is not limited to: various media capable of storing computer programs, such as a usb disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic disk, or an optical disk.
Those of ordinary skill in the art will understand that: although the present application has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments described in the foregoing embodiments, or equivalents may be substituted for elements thereof. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims (10)

1. A log storage method for a multi-core heterogeneous system comprises the following steps:
in a multi-core heterogeneous system comprising at least two processor cores with different architectures, storing logs of operating systems in the processor cores into a memory in real time;
monitoring the working state of each processor core, and switching to an emergency operating system when one or more processor cores are abnormal;
resetting other processor cores which do not have exception in the multi-core heterogeneous system, and transferring the logs stored in the memory to a memory;
the emergency operating system and the memory work in a safety function domain.
2. The multi-core heterogeneous system log storage method according to claim 1, further comprising: the system is initialized, a memory is divided into a plurality of spaces, different spaces and different processor cores are configured to be in the same hardware domain, and the spaces and the processor cores are used for storing log data of the processor cores of the multi-core heterogeneous system.
3. The multi-core heterogeneous system log storage method according to claim 2, further comprising: calling a configuration interface of an operating system to perform writing operation; and the configuration interface calls the buffer interface to write the log data into the corresponding memory space.
4. The multi-core heterogeneous system log storage method according to claim 1, further comprising: after the log is transferred and stored, the watchdog circuit is triggered to restart the multi-core heterogeneous system, and after the multi-core heterogeneous system is abnormal, the watchdog circuit is triggered to enable the output end of the watchdog circuit to send a reset signal to the multi-core heterogeneous system, so that the system is restarted.
5. The multi-core heterogeneous system log storage method according to claim 1, wherein the step of switching to an emergency operating system comprises: and calling a system switching function in the exception handling function to switch to the emergency operation system, wherein the exception handling function corresponds to an exception vector table of the system.
6. A multi-core heterogeneous log storage system, comprising:
the system anomaly detection module is connected with all processor cores in the multi-core heterogeneous system and used for detecting the running state of each processor core and sending a request signal to the emergency operation system when anomaly is detected;
the emergency operating system receives the request signal, starts and resets other processor cores which are not abnormal in the multi-core heterogeneous system, and transfers the log data stored in the memory to the memory;
and the memory is used for storing the log data when the multi-core heterogeneous system is abnormal.
7. The multi-core heterogeneous log storage system of claim 6, wherein the system anomaly detection module, the emergency operating system, and the memory operate in a functional security domain.
8. A multi-core heterogeneous chip comprising the multi-core heterogeneous system log storage system of claim 6 or 7.
9. An electronic device comprising a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the processor is configured to execute the computer program stored in the memory and implement the multi-core heterogeneous log storage method according to any one of claims 1 to 5.
10. A computer-readable storage medium having stored therein at least one instruction which is loaded and executed by a processor to implement the multi-core heterogeneous log storage method of any of claims 1-5.
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