JPS62202234A - Advance control system - Google Patents

Abstract

PURPOSE:To identify whether the instruction prefetch function is stopped or not in the processor side by providing a display means, which outputs a display signal indicating whether the instruction prefetch function is executed or not, in a storage device provided with an instruction prefetch means. CONSTITUTION:A storage device 1 provided with an instruction prefetch means 100 is provided with a display means 200; and when the means 100 executes the instruction prefetch function, a prefetch display signal (p) is outputted from the means 200, and a corresponding message is displayed on a processor 2. Consequently, it is identified whether the instruction prefetch function is stopped or not in the processor 2 side. Since the accuracy of the prefetch display signal is confirmed in the processor side as the result, the prefetch function can be stopped by a prefetch inhibiting signal ih; and a fetch request signal if is outputted from the processor in the prefetch function stop state to release the stop of the instruction prefetch function, thus preventing an information processing system from being left degraded in throughput.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] In an information processing system having an instruction preemption function, a means for displaying the execution state of the instruction preemption function is provided so that the instruction preemption function can be reliably recognized. Further, by making it possible to stop the instruction preemption function if necessary and canceling the stoppage in response to an instruction fetch request signal, it is possible to prevent the function from being left in a stopped state.

[Industrial application field]

The present invention relates to an improvement in a preemptive control method in a storage device having an instruction prefetch function.

An instruction preemption function has been widely adopted as a means of improving the processing capacity of information processing systems.

The instruction preemption function takes advantage of the fact that each instruction that makes up a program stored in a storage device is often extracted and executed by a processing device in the order of their addresses. Several instructions after the address are extracted and stored in advance to shorten the instruction reading time in response to a request from a processing device.

If such an instruction preemption function stops, the processing capacity of the information processing system will be significantly reduced, so there is a need for a means that allows a processing device to reliably identify whether or not the instruction preemption function has stopped.

[Conventional technology]

FIG. 3 is a diagram showing an example of a conventional advance control method in this type of information processing system.

In FIG. 3, a storage device 1 and a processing device 2 are connected to a bus 3.
connected via.

The storage device 1 is a storage unit 1) that stores instructions and data.
, a write register 12 that temporarily stores write data transmitted from the processing device 2, a read register 13 that temporarily stores instructions and data read from the storage unit 1), and an instruction prefetch function provided by the storage device 1. An instruction prefetch buffer 14 that temporarily stores instructions read out in advance from the storage unit 1), a prefetch control unit 15 that implements an instruction prefetch function, and an address register 16 that stores addresses for writing or reading transmitted from the processing device 2. Equipped with:

When the processing device 2 stores a write address in the address register 16 via the bus 3 and also stores write data in the write register 12 via the bus 3, the storage device 1 stores the write address in the address register 16 via the bus 3.
), the write data stored in the write register 12 is stored in the area corresponding to the write address stored in the address register 16.

Further, the processing word W2 is transferred to the address register 16 via the bus 3.
When successive addresses are accumulated in the storage device 1, the storage unit 1)
The commands and data stored in the read address corresponding area stored in the address register 16 are read out, temporarily stored in the read register 13, and then sent back to the processing device 2 via the bus 3.

Note that the prefetch control unit 15 updates the address stored in the address register 16 for instruction reading, sequentially reads out the instructions stored in the next address, and updates the address stored in the address register 16 to read the instruction.
The instructions are stored in the instruction prefetch buffer 14 via the instruction prefetch buffer 14.

In this state, when an instruction fetch request signal if for reading an instruction is transmitted from the processing device 2, the prefetch control unit 15 transfers the instruction stored in the instruction prefetch buffer 14 to the bus 3.
The data is sent back to the processing device 2 via.

[Problem that the invention seeks to solve]

As is clear from the above explanation, in the conventional advance control method, when the instruction preemption function provided in the storage device 1 is no longer executed, the time for successive commands from the storage device 1 increases, and the processing capacity decreases. However, the storage device 1 has no means for displaying the execution status of the instruction preemption function, and the processing device 2 has no choice but to assume that the instruction preemption function has stopped due to a decline in processing performance.

[Means for solving problems]

FIG. 1 is a diagram showing the principle of the present invention.

In FIG. 1, 1 and 2 are a storage device and a processing device that constitute an information processing system to which the present invention is applied.

Reference numeral 100 denotes an instruction prefetching means that implements an instruction prefetching function.

200 is a display means provided according to the present invention, which outputs a preemption display signal p indicating whether or not the instruction prefetch means 100 is executing the instruction prefetch function.

[Effect]

By reading the prefetching display signal p output by the display means 200, the processing device 2 can reliably identify the execution state of the instruction prefetching function of the instruction prefetching means 100.

Furthermore, in order to confirm the normality of the instruction prefetching means 10.0, it is possible to stop the instruction prefetching means 100, and furthermore, when the instruction fetching request signal if is transmitted from the processing device 2 while the instruction prefetching means 100 is stopped, The stopped state of the instruction preemption means 100 is immediately released, and there is no longer a risk that the information processing system will be left unattended with reduced processing capacity.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing a proactive control method according to an embodiment of the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

In FIG. 2, the flip-flop (FF) 17 is
It is provided as a display means 200.

Also in FIG. 2, the function of storing data from the processing device 2 to the storage device 1, the function of reading instructions and data from the memory word W1, and the function of prefetching instructions are executed in the same process as in FIG.

Note that when the prefetched instruction is accumulated in the instruction prefetch buffer 14, the prefetch control unit 15 sets the flip-flop 17 to the cent state. As a result, the flip-flop 17
The pre-emption indication signal p outputted by is set to logic "1".

The processing word W2 reads out the preemption display signal p output by the flip-flop 17 via the bus 3, analyzes the logic value, and if the logic value is set to "1", the preemption control unit 15 performs the instruction prefetch function. Identifies that you are running a logic “
If it is set to 0'', it is determined that the preemption control unit 15 has stopped the instruction preemption function.

Furthermore, in order to diagnose whether the preemption display signal p reliably indicates the execution state of the instruction preemption function, when the processing device 2 transmits the preemption prohibition signal ih to the storage device 1 via the bus 3, the preemption control An instruction preemption disabling flip-flop 151 is inserted in section 15 to disable instruction preemption. In such a case, the preemption control unit 15 sets the flip-flop 17 to a reset state. As a result, the preemption display signal p output from the flip-flop 17 is logic "0".
, and it is diagnosed that the preemption display signal p reliably indicates the operating state of the instruction preemption function.

In this state, when the processing device 2 transmits an instruction fetch request signal if to the storage device 1 in order to extract an instruction, the instruction preemption function stop flip-flop 15 is activated in the prefetch control unit 15.
1 is reset, the stopped state of the instruction preemption function is released, and execution of the instruction preemption function is started again through the above-described process. Therefore, the pre-emption control unit 15 is left in a non-functional state,
This prevents the processing capacity of the information processing system from becoming degraded.

As is clear from the above description, according to the present embodiment, the execution state of the instruction preemption function of the preemption control unit 15 in the storage device 1 is set to the flip-flop 17, and the preemption display signal p output from the flip-flop 17 is monitored. By doing so, it becomes possible to identify it from the processing device 2.

In addition, in order to diagnose the normality of the pre-fetch display signal p, it is possible to stop the instruction pre-fetch function, and the pre-fetch control unit 15 in the stopped state receives the instruction fetch request signal if from the processing device 2. As soon as the operation is stopped, the preemption control unit 15 is released from the stopped state, so that the preemption control unit 15 is prevented from being left in the stopped state, and the processing capacity of the information processing system is prevented from being degraded.

Note that FIG. 2 is only one embodiment of the present invention, and for example, the display means 200 is not limited to the flip-flop 17, and many other modifications may be considered; The effects of the present invention remain unchanged.

〔Effect of the invention〕

As described above, according to the present invention, in the information processing system, the processing device can reliably identify the execution state of the instruction preemption function by monitoring the preemption display signal outputted by the display means.

In addition, in order to confirm the normality of the pre-fetch display signal, it is possible to stop the pre-fetch function.Furthermore, when an instruction fetch request signal is transmitted from the processing device with the instruction pre-fetch function stopped, the instruction pre-fetch function The stopped state of the information processing system is immediately released, and there is no longer a risk that the information processing system will be left unattended with reduced processing capacity.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a diagram showing a advance control method according to an embodiment of the present invention, and FIG. 3 is a diagram showing an example of a conventional advance control method. In the figure, 1 is a storage device, 2 is a processing device, 3 is a bus,
1) is a storage unit, 12 is a write register, 13 is a read register, 14 is an instruction prefetch buffer, 15 is a prefetch control unit, 16
is an address register, 17 is a flip-flop (FF)
, 100 is an instruction preemption means, 151 is an instruction preemption function stop flip-flop, 200 is a display means, if is an instruction fetch request signal, ih is a preemption prohibition signal, p is a preemption display signal,
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Claims (2)

[Claims] (1) Storage device (1) equipped with instruction prefetching means (100)
) and a processing device (
2) An information processing system comprising: a display means (200) for displaying whether or not the instruction preemption means (100) is executing an instruction preemption function; provided in the storage device (1); A preemptive control system characterized in that a preemption display signal (p) outputted by the processor (200) can be read out from the processing device (2). (2) The instruction prefetching means (100) includes the processing device (
When the instruction preemption function (ih) is transmitted from the processing device (2), the instruction prefetch function is stopped, and in a state where the instruction prefetch function is stopped, the instruction fetch request signal (ih) is transmitted from the processing device (2).
2. The advance control method according to claim 1, wherein the function stop state is canceled when the signal if) is transmitted.