JPS58189748A - Storage device of state information - Google Patents

Abstract

PURPOSE:To perform debugging with high efficiency for a state information storage device of an electronic computer, by recording the state of information on the kind and the generation time of an error. CONSTITUTION:When a signel logic in an error generating signal group 9 is set at 1, a write enable signal 7 is delivered by the next clock signal 5. Then the state information 2 is written to a stack 1, and at the same time the contents of the group 9 are written at other position of the same address. The logic of an error generating signal 6 is set at 1 after the contents of the group 9 are written to the stack 1. This prevents the output of the signal 7 and inhibits the working of an address forming circuit 4. Therefore it is possible to understand the progress of generation of an error and the kind and the generating time of the error by checking the record of the stack 1.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention This invention relates to a status information storage device for an electronic meter.

Structure of conventional technology bK Conventionally, there was a device for this purpose, as shown in Figure 1.

In the figure, +11 is the status information stack, (2) is the status information, and (3) is the write enable (write enable).
ble II + 11 value - 1 path, (4) rt address generation circuit, (5) clock invitation signal, (6) rL error generation signal, (7) write enable signal, .81&fr address. Here, the state information @(2) refers to a state signal in which preset types of state No. 18 are arranged in a predetermined order among the state signals representing the state of each part of awakening + sadness - emotion, for example. If each part of Shape 418 indicates whether it is on or off with one hit signal each, then it is 16115 Qr.
status signals can be displayed in a 16-pit pattern. Also, error occurrence 'L f = 'F916+ is a predetermined range of errors detected by machine check, errors issued by program check, hardware errors, etc. This is a signal indicating that one of the 71 errors has occurred.

Operation of the prior art When the error occurrence signal (6) is logic "0" (indicating that an error has not occurred), the write enable control a11 circuit (3) outputs the tarok signal (5). write enable signal (7) and 1. and output the clock signal (
5) The state information @(2
) writes to stack (1). The write position is determined by the address (8), and the address generation circuit (4) is a pulse counter having a gr number field equal to the total number of addresses in the stack tl+, and the contents are divided by several digits per input of the clock signal. Since the state ↑^information (2) is incremented, the state ↑^information (2) is in the stack ill in order of time.
1 (7 is memorized.

When the error occurrence signal (6) becomes logic "1", the output of the write enable signal (7) is stopped, and the operation of the address generation circuit (4) is stopped.

Disadvantages of the prior art Since the conventional device is configured as described above, the status information (2) up until the moment the error occurs is well recorded, and it is possible to determine the progress that occurred before the error occurred. Although this provides an effective means for investigating whether the error occurred, the error itself and the status information (2) in the state in which the error occurred are not recorded.
There were times when it was difficult to ascertain the condition of the aircraft and take corrective action.

Purpose of the Invention The present invention is to eliminate all the drawbacks of the conventional ones as described in 1.
The overall object of the present invention is to provide a status information storage device capable of recording status information at the time when the error occurred.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will now be described with reference to the drawings. Second
The figure shows a block LA that accommodates one embodiment of the present invention, -A1
The same sign as 〆I is the same - or phase -! l] part, (9
) is predetermined for each error signal group, t or 4-
Contains all types of error signals. 11 is an OR circuit, (1
υ is a delay circuit.

If no error occurs in the operation nib-generating group 18 (9) of this defense, the signal logic of the output of the OR circuit + IO is "O" and the circuit in Figure 2 is the circuit in Figure 1. The operation is the same as when the logic of the error occurrence signal (6) is "0".

The logic of any signal in the error signal group (9) is “1”.
”, the write enable signal (7) is output with the next clock signal (5), the status information (2) is written to stack +11, and at the same time an error occurrence signal is sent to other bit positions at the same address. The contents of group (9) are written.

At this point, the output of the OR circuit +l□ is "1", but the error occurrence signal (6) is still kept at logic "0" because of the delay 101 path 0σ. After writing the contents of the error signal group (9) to the stack (11), the logic of the signal (6) becomes "1", which blocks the output of the enable signal (7) and prevents the operation of the address generation circuit (4). prohibit.

Therefore, if you examine the status information stack (11 records), you will find out the progress until the error occurred, the type of error that occurred,
Since the state at the time an error occurs can be known, debugging can be performed efficiently.

Effects of the present invention As described above, according to the present invention, failure analysis can be completed efficiently and in a short period of time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a device according to the present invention, and FIG. 2 is a block diagram showing an embodiment of the present invention. tl+...Status information stack, (2)...Status information, (3)...Write enable control circuit, (5)...
・Clock signal, (6)...Error occurrence signal, (7)
...Write enable signal, (9)...Error occurrence signal group. In addition, the same reference numerals in the figures refer to the same or corresponding parts. Agent Shin Kuzuno −

Claims (1)

[Claims] Means for sequentially writing a predetermined type of status information into a status information stack for each clock signal of a predetermined cycle, and means for sequentially writing a predetermined type of status information into a status information stack for each clock signal of a predetermined cycle, and a means for sequentially writing status information of a predetermined type into a status information stack when an error of any one of the predetermined types occurs. means for writing the error information at a position corresponding to the address # where the status information is written in response to a clock signal; and means for stopping writing to the status information stack after the writing of the error information is completed. A state information storage device comprising: