JPS6054059A - Storage device - Google Patents

Abstract

PURPOSE:To detect accurately the malfunction of a storage address driving circuit even if a storage address including ECC checking method, by driving storage address information, which are given to plural storage parts constituting a word, with one storage address driving circuit. CONSTITUTION:When a storage address driving circuit 1 of a certain storage block 10 is driven by a start signal, input storage address information are supplied to individual storage parts 2 in the block 10 at a time, and word information of total 39 bits (one word) consisting of a 32-bit data part and a 7-bit check bit part is read out. Simultaneously, input storage address information are supplied to a parity bit generating circuit 20 to generate a parity bit corresponding to them. This parity bit, data read out from the block 10, and check bits are given to a storage address including ECC error detecting circuit 30, and a one-bit error of data, a storage address error, and a multi-bit error are detected. That is, even if the storage address including ECC (error detecting check bit) checking method is applied, the malfunction of the circuit 1 is detected accurately.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a memory device, and more particularly to a memory device that effectively detects malfunctions in a memory address drive circuit and reads information without errors.

[Background of the invention]

One of the causes of errors when writing and reading information to and from a storage device is malfunction of a storage address drive circuit used to drive storage address information (address information) provided to a storage section. Conventionally, an odd-even test method has been widely used as a method for detecting malfunctions of the memory address drive circuit. This testing method is a method of performing an odd-even test on the memory address information output from the memory address drive circuit, but generally there are N memory devices that store data in units of words (N corresponds to the number of bits in one word). ), it is composed of a large number of memory blocks (memory packages) including a memory section and a memory address drive circuit, so it is necessary to provide an odd-even check circuit for each memory block, making the entire odd-even check circuit large-scale. It has some drawbacks.

On the other hand, as a method for detecting errors in memory address information, there is a "memory address-inclusive Jj, E CC inspection method." This creates m-bit error correction/n pino 1 ~ error detection check bits (FCC) from the write data and storage address information, adds the check bit 1 ~ to the aokomi data and stores it, and when reading, This method also detects errors in storage addresses from read data, check bits, and storage address information.

Although this testing method has the advantage that an error detection circuit can be provided for each storage device, it is difficult to detect errors in the original storage address information, for example, the storage address information sent from the processing device to the storage device. Although it is effective, if the memory address drive circuit is divided into each memory part that makes up a word, like the memory address drive circuit in a conventional memory block, a malfunction of one drive circuit may result in an error in the memory address. Because of the lack of regularity, it was ineffective in detecting errors in the drive circuit portion.

[Object of the Invention] An object of the present invention is to provide a memory device that makes it possible to easily and correctly detect malfunctions of a memory address drive circuit even when a memory address-inclusive FCC inspection method is applied. [Summary of the Invention] The present invention The key point of this is that by driving the memory address information given to multiple memory units constituting a word with a single memory address drive circuit, memory address errors including errors in the memory address drive circuit can be detected by the memory address-inclusive FCC inspection circuit. It is detected by

[Embodiments of the invention]

FIG. 1 shows a block diagram of one embodiment of the invention.

2. Figure 1 only shows the readout system of the storage device.
Components not directly related to the present invention, such as activation signals, are omitted.

In FIG. 1, 10 is a storage block (memory package) that stores information in units of words, and the storage device has a large number of such storage blocks 10.

Each memory block 10 consists of one memory address drive circuit 1 and a plurality of memory units 2. The number of storage units 2 corresponds to the number of pins constituting a word, and in this embodiment, one word -
Since there are 39 bits, one memory block lo includes 39 memory units M1 to M39. It is assumed that each storage unit 10 has a 1-pil/address storage format. 20 is a parity bit 1 generation circuit, which generates a parity bit of storage address information. 30 is F including memory address
This is a CC error detection circuit, which is given the read information from the memory block 10 and the parity bit of the memory address information from the parity bit generation circuit 20, and detects 1-bit errors in data, memory address errors, and multiple pin 1 to error signals. Output.

FIG. 2 shows a test matrix used in the FCC error detection circuit including memory addresses of this embodiment. In FIG. 2, bytes O-3 are the data portion within the word, byte C (7 bits) is the check bit portion within the word, and bit A is the parity bit of the storage address information.

The outline of the operation in FIG. 1 is as follows. When an activation signal (not shown) is applied to the memory address drive circuit 1 of the memory block 10, the corresponding memory address drive circuit 1 is driven, and the input memory address information is sent to each memory section 2 in the corresponding memory block 10 all at once. The word information of 32 bits in the data part and 7 bits in the check bit part, totaling 39 bits, is read out. At the same time, the input storage address information is also supplied to the parity pit generation circuit 20, and a parity bit for the storage address information is generated. The data read from the memory block 10, the check bit 1-1, and the memory address parity bit generated by the parity pit generation circuit 20 are given to the error detection circuit 30, and the error detection circuit 30 detects a 1-bit error in the data.
Storage address errors and multiple bit errors are checked.

Next, a specific example will be explained. In order to simplify the explanation, the memory address information has a structure of 8 bits 1 to 1, and the memory part 2
It is assumed that information whose data portion is all rr Ot+ is stored in all memory addresses.

Now, if a read operation is performed from the memory address "ooooooooo" in each storage unit 2, the data part in the read information is all rr Ou, and the test pins 1 to 1 are all "
]”.Similarly, the memory address is “oooo.”

When a read operation is performed from "001", the data portion in the read information is all "0", and the test bit 1- is all "o". In either case, the error detection circuit 3
0, no error is detected.

Next, when reading from the memory address "ooooooooo", if "00000001" is written to each memory section 2 as memory address information due to an error in the memory address drive circuit 1, the read information will be checked if the data section is all "0"'. Part 1 also becomes all "o". On the other hand, the error detection circuit 30 receives the correct memory address "ooo" from the parity pit generation circuit 20.
oooooo'' is given, the syndrome becomes ``11111111'', an error in the storage address is detected, and a storage address error signal is output.

In the following, the error in bit 7 of the memory address has been explained, but errors in other bits can be similarly detected as errors in the memory address. Also, the data section is all par 0.
The same applies to other than ″′.

Further, an error in the storage address drive circuit 1 during writing can also be detected as an error in the storage address in the same way as during reading.

In this embodiment, one word is made up of 39 bits (32 bits in the data section and 7 bits in the check bit section), but it is only necessary to provide memory address information to all the memory sections constituting the word using one memory address drive circuit. If, ■ Pi I in the word ~
The number may have other values.

Similarly, in this embodiment, the storage section has a 1-bit 1-address configuration, but it may also be configured to have a plurality of bits. Further, as long as the test matrix includes memory addresses, a test matrix other than those shown in FIG. 2 may be used, for example, test matrixes 71 to 71 for multiple bit error correction may be used. Furthermore, the memory address information is 8 pins! Needless to say, it may be anything other than ~.

〔Effect of the invention〕

As is clear from the following two explanations, according to the present invention, one memory address drive circuit provides memory address information to all memory units constituting a word. Errors can be detected by the error detection circuit of the FCC including the memory address as if all bits of the memory address were similarly read from a memory address different from the intended purpose, and the memory address drive circuit can be inspected reliably while minimizing the increase in logic scale. It becomes possible.

Furthermore, in the conventional method of performing an even-even check on memory addresses, it is true that it is impossible to match the time zone of the memory address required by the storage unit with the time zone for performing the odd-even check. In the present invention, since read information is determined and error detection is performed depending on whether the memory address is a correct value during the time period required by the memory section, more accurate error detection of the memory address drive circuit is possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a diagram showing an example of an inspection matrix used in the embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Memory address drive circuit, 2...Storage part, 10...
- Memory block, 20... Memory address parity pit generation circuit, 30... FCC error detection circuit including memory address.

Claims (1)

[Claims] (1) A storage device that creates check bits for m-bit error correction and n-bit error detection from write data and memory address information, adds the check bits 1- to the write data, and stores the result as information in word units. , a plurality of storage units that store information in units of words; a storage address drive circuit that is driven by input storage address information and provides storage address information in common to the plurality of storage units; and the input storage address A parity bit generating circuit that generates a parity bit of information, and inputting the information of the second 811th position read from a plurality of storage units according to the memory address information and the parity bit generated by the parity bit generating circuit. , an error detection circuit that detects errors in storage addresses, including malfunctions of the storage address drive circuit.