JPH02252043A - External transfer circuit inspecting system - Google Patents

Abstract

PURPOSE:To quantitatively execute the test of an external transfer circuit and to attain the execution of a test for a long time by providing an expected value forming circuit and a comparator into the external transfer circuit. CONSTITUTION:The expected value forming circuit 34 and the comparator 35 are provided in the external transfer circuit 3, a data pattern previously formed in the circuit 34 is stored in a storage device 2, data are sent to an external device 4 through the circuit 3 and compared with the expected value formed by the circuit 34 by the circuit 35, and when both the values are different, the coincidence is detected as an error. When the error is detected, the data generating the error, the expected value of the data and the address of the buffer storing the error data are stored. The circuit 34 forms plural kinds of expected values and executes plural data pattern tests to improve the reliability of the circuit 3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention particularly relates to an external transfer circuit verification method for transferring data to an external device.

[Conventional technology]

Traditionally, computer graphics was created using Nikkei CG (1
988,6) r As described in CGJ as a supercomputer that suppresses the era of symbiosis and complementarity, data was sent through high-speed channels. In addition to a monitor that displays graphics, a storage medium such as a disk device can be connected to a channel. Therefore, testing of the data transmission section (channel) requires sending data to the storage medium once and then testing it again. This is done by reading the data and testing whether there are any errors in the data.

[Problem to be solved by the invention]

In the conventional technology described above, data transfer is performed via a channel, and a disk device or the like can also be connected. However, unlike the channels described above, the external transfer circuit targeted by the present invention is a circuit that directly transfers data in a storage device to an external device, and has a large transfer capacity and is compatible with storage media such as disk devices. Connection is difficult.

The external device described here is like a monitor, and the data is image data, and the accuracy of the data can only be checked by visually checking the image on the monitor. Visual checking has its own limitations, lacks verification accuracy, and is difficult to conduct long-term tests.

An object of the present invention is to provide an external transfer circuit verification method that quantitatively tests such external transfer circuits and enables long-term testing.

Another purpose is to make it possible to retain information necessary for investigating the cause of the failure when a failure in the external transfer circuit is discovered through the test.

Furthermore, another objective is to enable multiple types of testing.

[Means to solve problems]

In order to achieve the above purpose, an expected value generation circuit and a comparison circuit are provided in the external transfer circuit, a data pattern generated by the expected value generation circuit is stored in advance in the storage device, and the data is transferred externally. The expected value generated by the expected value generation circuit is compared with the expected value generated by the expected value generation circuit by the comparison circuit, and a mismatch is detected as an error.

Furthermore, when an error is detected, the data in error, the expected value for the data, the address of the buffer in which the data in error was stored, etc. can be held.

Furthermore, the expected value generation circuit can generate multiple types of expected values, test multiple data patterns, and improve the reliability of the external transfer circuit.

[For production]

External transfer: jtFrjR path transfers the data read from the storage device to the external device at a very high speed.1 The expected value generation circuit generates the expected value in accordance with the sending of the external transfer data, and the comparison circuit generates the expected value. A comparison is made between the externally transferred data and the expected value. Therefore, verification of external devices is performed with great accuracy. In addition, everything is done using hardware and software.
Since it does not involve human visual inspection, long-term tests lasting several hours are possible.

Furthermore, since it is possible to know the error data, expected value, and buffer address where the error data was stored when the failure occurred, it is possible to easily find the cause of the failure.

Furthermore, a plurality of types of one expected value can be generated, and the reliability of the external transfer circuit can be improved by the test.

【Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

In the explanation, the external transfer operation will be explained first, and then the method for verifying the external transfer circuit of the present invention will be explained.

External transfer tL is performed by executing an external transfer command. The external transfer command is a command to transfer the data continuously stored in the storage device 2 to the external device M4 at a certain pitch, and the storage device in which the data is stored! 2, and the amount of data to be transferred. In this embodiment, the data sent to the external device 4 is 4.
Each byte.

1st Il! FIG. 1A is a block diagram showing the entire system for performing an external transfer operation. The external transfer command is decoded by the instruction processing bag [1, data is read from the storage device 2, partially buffered by the external transfer circuit 3, and transferred to the external device 4 at a constant pitch.

FIG. 3 shows a part of the storage device 2. As shown in FIG. Figure 4 shows the external transfer circuit 3, and Figure 5 shows the external transfer control unit 3.
It shows 0.

When the command processing device 11 decodes the external transfer command, it sends the external transfer command to the storage device 2 to start an external transfer operation. In the storage device 2, the external transfer command register 200 is set to '1' by the external transfer command, and the external transfer start storage address and transfer amount are respectively set in the storage read address register 201. The remaining transfer amount is set to 202. It also sends an external transfer start signal to the external transfer circuit 3 to initialize the buffer write address register 300 and buffer read address register 301 of the external transfer control unit 30.

In the storage device 2, the external transfer command register 200 is set to 1.
', an external transfer instruction is sent to the external transfer circuit 3 at one cycle pitch, and the data at the address indicated by the memory read address register 201 is read from the storage data section 220 and sent to the external transfer circuit 3 as buffer write data. and memory read address register 2
The adder 211 adds the contents of 01 to +32. The contents of the column transfer amount register 202 are subtracted by -32 by a subtracter 212. Here, 1
The width of the buffer write data sent in each cycle was set to 32 bytes.

In the external transfer circuit 3, according to an external transfer instruction.

A buffer write instruction and a buffer write address are sent to the external transfer data buffer 31, and data in the external transfer data buffer 31 is written. 6 Writing to the external transfer data buffer 31 is performed from address O, Write buffer write data width 32 bytes at a time. Also, the buffer write address register is added to the adder 31.
0 gives +32.

By repeating the above operation, the buffer read determination circuit 32
1 is stored in the external transfer data buffer 31.
When it is detected that the data is stored in the buffer readable register 303, the buffer readable register 303 is set to 1'.

Furthermore, when the external transfer data buffer 31 becomes full, the data amount control 320 detects this, sends a buffer FuLL signal to the storage device 2, and suppresses sending of an external transfer instruction.

When the buffer readable register 303 becomes 1', the pitch signal generated by the buffer read pitch control 322 sends a buffer read instruction and a buffer read instruction, reads 4 bytes of data from the external transfer data buffer 31, and transfers the data to the external transfer data register. Set to 32. Further, the contents of the buffer read address 301 are incremented by 4 by an adder 311. Thereafter, the above operation is repeated to sequentially send the 4-byte data set in the external transfer data register 32 to the external device 4.

The data amount control 32 indicates that an empty space has been created in the external transfer data buffer 31 due to data transmission to the external device 4.
If it is detected as 0, the sending of the buffer FuLL signal is stopped and data writing to the external transfer data buffer 31 is restarted. Here, since the external transfer data buffer 31 is written from the address that has been read, the buffer write address register 300. The contents of the buffer read address register 301 are controlled to wrap around to 0'.

When the end determination 230 detects that the content of the column transfer amount register 202 has become 10j, the instruction processing device 1. An external transfer end signal is sent to the external transfer circuit 3. Furthermore, in the external transfer circuit 3 that receives the external transfer end signal, the buffer read determination circuit 321 determines the end of data transmission to the external device 4, and resets the value of the buffer read enable register 303 to 0'. This completes the external transfer operation.

Next, a method for verifying the external transfer circuit 3 will be explained.

First, the hardware configuration prepared to perform the test will be explained. The expected value generation circuit 34 includes a counter a341, a counter l342 . . . . and the test pattern register 340. The counter a341, the counter J342, . . . generate different data patterns, and one of them is selected depending on the value of the test pattern register 340 and set in the expected value data register 33.
The width is 4 bytes, which is the same as the external transfer data. Comparison circuit 35
compares the contents of the external transfer data register 32 (external transfer data) and the contents of the expected value data register 33 (expected value data), and outputs 0' if they match, and 1' if they do not match. . The error check register 36 sets the output result of the comparison circuit 35 in response to an error check instruction. Finally, the test mode register 304 is set to 11' only when performing a test, and is set to '0' when normally executing an external transfer operation.

When performing a test, first write 'I' in the test mode register.
, and further sets the value of the test pattern register 340 in order to select the data pattern of the expected value. Here, it is assumed that the counter a341 is set to generate an expected value.

Since the expected value pattern generated by the counter a341 is fixed, the instruction processing device tl generates data of the same pattern and stores them continuously in the storage device 2.

External transfer operation is executed in this state. The external transfer start storage address and transfer amount at this time are stored in the counter a34.
Data with the same pattern as the expected value generated in 1 was stored. Set to the start address of the storage data section and the amount of stored data.

The buffer write address register 300 and the buffer read address register 301 are initialized by an external transfer start signal generated by starting an external transfer operation, and at the same time, the expected value data register 33 is initialized.

When data is written to the external transfer data buffer 31 and the value of the buffer readable register 303 becomes '1',
Data is read from the external transfer data buffer 31, and an expected value update instruction is sent to the counter a34.
A value of 1 is set in the expected value data register 33. Further, the comparison circuit 35 compares the 4-byte data set in the external transfer data register 32 and the 4-byte data set in the expected value data register 33. The comparison result is stored in the error check register 36 according to the error check instruction.
Store in. The value of error check register 36 is '1'
When this happens, the external transfer control unit 30

Suppresses sending of buffer read instruction 1 expected value update instruction and error check instruction. As a result, updating of the value of the external transfer register 32, the value of the expected value data register 33, the value of the buffer read address register 301, and the value of the error check register is suppressed. That is, the external transfer data, expected value, and address of the external transfer data buffer 31 at the time of error occurrence can be known.

Furthermore, an error report is sent to the memory bag [12] according to the value 11' of the error check register 36. In the storage device 2, in response to the error report, the external transfer command register 2 is
00, and the instruction processing device 1. The end of the external transfer is reported to the external transfer circuit 3.

When testing on an actual system, settings of the test mode register 304 and test pattern register 340, storage of the expected value data pattern in the storage device 12, issuance of an external transfer instruction, and determination of whether an error has occurred after execution of the instruction are necessary. A test program is used to check and read the value of the external transfer register 32, the value of the expected value data register 33, and the value of the buffer read address register when an error occurs. Not only is it possible to perform quantitative verification, but also long-term testing is possible.
This makes it easier to find the cause of a failure.

〔Effect of the invention〕

According to the present invention, it is possible to easily and quantitatively verify the operation of an external transfer circuit, which is difficult to test because it sends data to an external device, using a test program. In addition, long-term tests (heat run tests) can be easily performed, and in the event of an error, information such as addresses and data can be obtained, making it easier to find the cause of the failure. There is.

[Brief explanation of drawings]

FIG. 1 is an overall configuration diagram of an embodiment of the present invention, FIG. 2 is a configuration diagram of a conventional system for data transfer via channels, FIG. 3 is a circuit diagram showing part of a storage device, and FIG. The figure is a circuit diagram showing an external transfer circuit. FIG. 5 is a circuit diagram showing details of the external transfer control section, and FIG. 6 is a circuit diagram showing the expected value generation circuit. DESCRIPTION OF SYMBOLS 1... Instruction processing device, 2... Storage device, 3... External transfer circuit, 4... External device, 5... High speed channel, 6... Disk device, 200... External transfer Command register, 201... Memory read address register, 202... Column transmission amount register, 220... Storage data section, 30... External transfer control section, 31... External transfer data buffer, 32... - External transfer data register, 33... Expected value data register, 34... Expected value generation circuit, 35... Comparison circuit, 36... Error check register, 300... Buffer write address register, 301... ...Buffer read address register, 302...External transfer instruction register, 303...Buffer readable register, 304...Test mode register, 340...Test pattern register. Eye 1.5 4th eye Akira 5th eye

Claims (1)

[Claims] 1. An instruction processing device having functions such as decoding and execution of instructions, data transfer and calculations accompanying execution of instructions;
A storage device that transfers data to and from the instruction processing device and holds the data, and an external transfer circuit that has a function of transmitting data stored in the storage device to an external device. A comparison circuit is provided to compare the data sent to the external device with an expected value, and the expected value data pattern is stored in the storage device in advance, and the data pattern is sent to the external device and compared with the expected value in the comparison circuit. An external transfer circuit verification method is characterized in that a mismatch is detected as an error. 2. An external transfer circuit verification method according to claim 1, characterized in that upon error detection, data in which an error occurs and an expected value for the data are held. 3. An external transfer circuit verification method, characterized in that the external transfer circuit according to claim 1 is provided with an expected value generation circuit to generate a plurality of types of expected values.