JP2727947B2 - Address trace method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address tracing device for collecting an execution address history of an information processing device.

[0002]

2. Description of the Related Art A first conventional address trace device comprises:
All addresses of instructions to be executed are stored as trace information. Therefore, there is a problem that a large amount of storage circuits are required because the addresses of sequentially executed instructions are also included in the trace information.

As a technique for improving this, there are second and third devices described below with respect to microprogram control.

The second conventional address tracing device reproduces an execution process by keeping all instructions to be executed whether they are branch instructions or not. For example, JP-A-59-194245 discloses that for every instruction to be executed, a bit indicating whether or not the instruction is a branch instruction is provided.
A device that stores two bits of a bit indicating a trace stop position as trace information and knows an execution process by following a program in the reverse direction while referring to a bit indicating a branch instruction or not from the trace stop bit and its address is described. Have been. Since only a 2-bit storage circuit is required for one instruction, a smaller amount of storage circuits is required than in the first conventional method. However, this method has a problem in that when there are a plurality of branch instructions to the same address, the position of the branch source cannot be determined in principle. In a microprogram, it may be possible to restrict multiple branch instructions from having the same branch destination address.However, in a normal computer program, this restriction has the problem that subroutines cannot be called from different places. is there.

A third conventional address tracing device stores a pair of a branch address and a branch destination address only when a branch occurs, utilizing the fact that the execution of instructions proceeds in a sequential order in principle. Is what you do. For example, Japanese Unexamined Patent Application Publication No. 60-189538 discloses an address storage means for storing the address of an instruction being executed, an address conversion means for converting its output as instructed, and an output from the address storage means. Address comparison means for comparing the post-translation address of the previous address with the converted address and outputting the result; and address storage means for storing the pre-conversion address of the address conversion means and the address of the address storage means according to the result of the address comparison means. A device implemented with is described. If an instruction to add 1 to the pre-translation address is given to the address translating means and an instruction to store the address is given to the address comparing means, the branch source address and the branch destination address are obtained only when a branch occurs in the address storage means. Address 2
One address can be stored as a set, and address trace can be performed with a small amount of storage means without storing redundant trace information.

[0006]

In the first conventional address tracing method, since the addresses of sequentially executed instructions are also included in the trace information, a large amount of storage circuits are required for redundant trace information. There was a problem of doing.

In the second conventional address trace method,
When there are a plurality of branch instructions having the same address, there is a problem that the position of the branch source cannot be determined.

In the third conventional address trace method,
A storage circuit for storing two addresses of a branch source address and a branch destination address for one branch is required. Further, if it is attempted to arrange only the address storage means in another block, for example, a board or a chip in order to increase the capacity of the address storage means, the number of signal lines required for connection increases to twice the number of address bits. There was a problem that it would.

[0009]

In order to solve the above-mentioned problems, in the address trace method according to the present invention, execution control means for executing a program and history of the program executed by the execution control means are stored. Trace mode holding means for holding a trace mode indicating whether or not to be taken; branch detection means for detecting whether or not the execution control means is executing a branch instruction; Trace instruction means for instructing a tracing operation in accordance with an instruction from the branch detection means, address output means for outputting the address of an instruction to be executed next to the branch instruction under the control of the trace instruction means, and Trace storage means for storing an address as a trace address.

An output address selecting means for selecting and outputting either a target address when the execution control means accesses an external circuit or a trace address from the address output means under the control of the trace command means; If the address from the address output means is a trace address, a trace storage means for storing the address is provided.

[0011] Further, there is provided an extended storage means connected to the trace storage means, and when the trace information stored in the trace storage means reaches a certain amount, the trace information of the area is transferred to the extended storage means. , Reuse the area.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the first example of the address trace method of the present invention will be described.
Will be described in detail with reference to the drawings.

Referring to FIG. 1, the address tracing method according to the first embodiment of the present invention employs an execution control means 110.
, A branch instruction detecting unit 120, a trace mode holding unit 130, a trace instruction unit 140, an address output unit 150, and a trace storage unit 200.

The execution control means 110 executes the program and outputs the currently executed instruction code to the signal line 112 and the instruction address to the signal line 115, respectively.

The branch detection means 120 detects whether or not the instruction code sent from the signal line 112 is a branch instruction, and outputs the result to a signal line 124.

The trace mode holding means 130 is connected to the signal line 1
In accordance with the control signal from 33, a trace mode for determining whether or not to trace the currently executing program is held and output to the signal line 134.

Trace instructing means 140 receives signals from signal lines 124 and 134, and if signal line 124 indicates the detection of a branch instruction and signal line 134 indicates an instruction to be in the trace mode. A control signal instructing a trace operation is output to the signal lines 145 and 142 at appropriate timing.

Address output means 150 stores an instruction address sent from signal line 115 in accordance with a trace operation instruction from signal line 145, and stores the stored contents on signal line 1.
52.

Trace instruction means 140 issues a trace operation instruction on signal line 145 at the next clock after the completion of the branch instruction.
, The address of the signal line 115 indicates the address of the instruction following the execution of the branch instruction.

The trace storage means 200 sequentially stores the addresses output to 152 in accordance with a trace operation instruction from the signal line 142.

When the address output means 150 outputs the storage address to 152, the trace command means 140 outputs a trace operation instruction to 142, so that the address stored in the trace storage means 200 is the next address after executing the branch instruction. This is the address of the instruction, which will be the trace address.

Next, the operation of the first embodiment of the address trace method of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 2, in a program to be executed, an address is assigned to one instruction in word units. It is also assumed that an address having a blank instruction content stores an instruction that is neither a branch instruction nor an external access instruction.

It is also assumed that the conditions A and B of the conditional branch instruction in the program change as shown in FIG.

First, the trace mode holding means 130 is set to a trace mode by a signal line 133 in advance to set a mode for tracing a program. The setting of the trace mode holding means 130 may be performed by an instruction of a program, or may be performed by an external service processor or the like. This allows
The signal line 134 outputs an instruction indicating that the mode is the trace mode.

When the execution control means 110 executes the instruction at the address 100, the instruction code at the address 100 is output to the signal line 112.
Numeral 20 does not instruct the signal line 124 to detect a branch, and the state does not change in other means. When this instruction ends, the instruction address “address 101” is output to the signal line 115.

Next, the execution control means 110 executes the branch instruction at address 101. At this time, the code of the branch instruction is output to the signal line 112, the branch detection means 120 detects that the instruction is a branch instruction, and the signal line 124 indicates that "branch instruction has been detected".
To the effect. The trace instructing means 140 is ready to instruct a tracing operation at the time when the instruction is completed according to the instructions on the signal lines 124 and 134. When this instruction is completed, the instruction address becomes address 105 by branching, and the signal line 1
The address “105” is output to 15, and the trace command means 140 outputs a trace operation instruction to the signal line 145.

The address output means 150 responds to the instruction of the trace operation of the signal line 145 and outputs the address "1" of the signal line 115.
05 is stored, and the address “105” is stored in the signal line 152.
Address "is output.

The trace storage means 200 stores the address "105" on the signal line 152 as a trace address in accordance with the instruction on the signal line 142.

Next, the execution control means 110 executes the instruction at address 105. Since the instruction is not a branch instruction, no branch instruction is detected, and when the instruction ends, “106” is output to the signal line 115 as an instruction address.

Next, the execution control means 110 executes the conditional branch instruction at address 106. As in the case of the branch instruction at the address 101, the branch detection means 120 detects the branch, and the trace command means 140 is in the ready state. When the instruction is completed, the instruction address becomes “address 102” and the address output means 1
Reference numeral 50 stores an address “102”, and the address storage unit 200 additionally stores “address 102” as a trace address.

In this way, the address of the instruction executed after the branch instruction, that is, the address of the branch destination, can be sequentially stored in the trace storage means 200 as the trace address.

Referring to FIG. 4, the time and instruction address 115 when the program of FIG.
, A branch instruction 124, a trace command 145, an output address 152, and a change in the state of the trace storage unit 200. However, in this figure, it is assumed that one instruction is executed in one unit time.

It should be pointed out that the address of the next instruction is stored as a trace address even when the condition is not satisfied and the branch is not taken by the conditional branch instruction. Shows this. Time 14
At the time point, the words in the trace storage means 200 are “105”, “102”, “107”,
“Address 105” and “Address 102” are stored. This is the branch destination address of all executed branch instructions. Considering that the execution of the program starts from address 100 and has branch instructions at addresses 101, 106 and 108 together with this information, it can be analyzed that the program has been executed as follows. That is, after address 100, 101
The address is executed, the address 101 branches to the address 105, then the address 106 is executed, and from the address 106 to 1
Branches to address 02, then 103, 104, 1
Execution is performed at addresses 05 and 106. And this 10
With the branch instruction at address 6, no branch occurs, and addresses 107 and 108 are subsequently executed. Then, it can be analyzed that the address 108 branches to address 105 and the next address 106 branches to address 102.

The number of words in the trace storage means 200 used in the first embodiment is 5, and the conventional first method requires 14 words which are the same as the time. Therefore, the number of storage circuits is reduced to about 36%. You can do it. In the third conventional method, 8
The need for words means that the memory circuit could be reduced to about 63%. Further, it is possible to easily determine a branch from a plurality of branch sources to the same address, which cannot be determined by the conventional second method, that is, a branch from addresses 101 and 108 to address 105 in this example.

Next, a second embodiment of the address trace method of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 5, the address tracing method according to the second embodiment of the present invention includes an execution control unit 110 and a branch instruction detection unit 120 in a central processing unit 100.
, A trace mode holding unit 130, a trace instruction unit 140, an address output unit 150, and an output address selection unit 160. In addition, the central processing unit 1
00, the trace storage means 200 and the external circuit 3
00. As the external circuit 300, for example, a storage circuit or a peripheral circuit can be connected.
Here, execution control means 110, branch instruction detection means 12
0, trace mode holding unit 130, the trace command means 140, address output means 15 0 and trace storage means 200, those having the same functions as those of the first embodiment.

The external address signal line 410 outputs an external address when the central processing unit 100 accesses an arbitrary external circuit 300.

When the execution control means 110 accesses the external circuit 300, its target address is output to the signal line 116.

The output address selecting means 160 is connected to the signal line 1
45, the signal line 116
, Or one of the trace addresses output from the address output means 150 to the signal line 156 is selected and output to the external address signal line 410. When the signal line 145 instructs the trace operation, the trace address of the signal line 156 is set.
16 is selected. Further, information for discriminating which one is selected and output is output to the address identification signal line 420. Address identification signal line 42
0 is connected to the trace storage means 200 and the external circuit 300.

The trace storage means 200 is connected to the external address signal line 410 and the address identification signal line 420. When the trace identification signal line 420 indicates a trace address, the trace address is transmitted from the external address signal line 410 to the trace address. Receiving and storing sequentially.

Referring to FIG. 6, the time when the program of FIG.
, An external circuit address 116, a branch instruction 124, a trace command 145, a trace address 156, an external address 410, an address identification signal 420, and a change in the state of the trace storage unit 200. However, in this example, the external access command is not completed until there is a response from the external circuit 300, and the external circuit 300 returns a response within one unit time after the address is output to the external address signal line 410, and Instructions are assumed to execute one instruction in one unit time.

At time 3, a write command to the external circuit at address 105 and a trace output at address 105 are simultaneously generated, so that the trace output is executed with priority.
Writing to the external circuit is executed at time 4. This event also occurs at time 13. On the other hand, at time 9,
Since no trace output is generated, the write instruction to the external circuit is executed without waiting.

In the address trace system according to the second embodiment, the central processing unit 100 sends the trace storage unit 2
By sharing a signal line for outputting a trace address to the external address signal line 410 with the central processing unit 1
There is an advantage that 00 input / output signal lines can be reduced.

Next, a third embodiment of the address trace method of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 7, the address tracing method according to the third embodiment of the present invention employs a trace storage unit 200.
The configuration is the same as that of the second embodiment except that the extended storage means 210 is connected to the.

The extended storage means 210 is connected to the trace storage means 200 by a signal line 201. When the trace information in the trace storage unit 200 reaches a certain amount, the trace information in that area is stored in the extended storage unit 210.
By reusing the transferred area in the trace storage means 200, a larger amount of trace information can be stored. This third
For example, the trace storage unit 2
00 may be constituted by a high-speed and low-capacity memory device, and the extended storage means 210 may be constituted by a low-speed and large-capacity disk device.

[0048]

As described above, according to the present invention, by storing the next address of an executed branch instruction in a trace storage means as a trace address, the number of storage circuits can be reduced as compared with the conventional address trace method. There is.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a first embodiment of an address trace method according to the present invention.

FIG. 2 is a diagram illustrating an example of a program used to explain an operation of the present invention.

FIG. 3 is a diagram illustrating an example of states of conditions A and B of a conditional branch instruction at the time of executing the program of FIG. 2;

FIG. 4 is a timing chart showing an operation when the program of FIG. 2 is executed in the first embodiment of the present invention.

FIG. 5 is a block diagram showing a second embodiment of the address trace method of the present invention.

FIG. 6 is a timing chart showing an operation when the program of FIG. 2 is executed in the second embodiment of the present invention.

FIG. 7 is a block diagram showing a third embodiment of the address trace method of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 Central processing unit 110 Execution control means 120 Branch instruction detection means 130 Trace mode holding means 140 Trace command means 150 Address output means 200 Trace storage means 210 Extended storage means 300 External circuit

Claims (4)

(57) [Claims] 1. An execution control means for executing a program, a trace mode holding means for holding a trace mode indicating whether or not a history of a program executed by the execution control means is taken; Branch detection means for detecting whether or not the control means is executing a branch instruction; trace instruction means for instructing a trace operation in accordance with instructions from the trace mode holding means and the branch detection means; Address output means for outputting only the address of an instruction to be executed next to the branch instruction even when not branching under control of the command means; and trace storage means for storing the address from the address output means as a trace address. An address trace method comprising: 2. An execution control unit for executing a program, a trace mode holding unit for holding a trace mode indicating whether or not a history of the program executed by the execution control unit is taken; Branch detection means for detecting whether or not the control means is executing a branch instruction; trace instruction means for instructing a trace operation in accordance with instructions from the trace mode holding means and the branch detection means; Even when the branch is not taken under the control of the command means, only the address of the instruction executed next to the branch instruction is traced.
Address output means for outputting as an address, and an output address for selecting and outputting one of a target address when the execution control means accesses an external circuit or a trace address from the address output means under the control of the trace command means. An address tracing method comprising: selecting means; and trace storage means for storing an address from the address output means if the address is a trace address. 3. An extended storage unit connected to the trace storage unit, wherein when the trace information stored in the trace storage unit reaches a certain amount, the trace information of the area is transferred to the extended storage unit. 2. The address trace method according to claim 1, wherein said area is reused. 4. An extended storage unit connected to the trace storage unit, wherein when the trace information stored in the trace storage unit reaches a certain amount, the trace information of the area is transferred to the extended storage unit. 3. The address trace method according to claim 2, wherein said area is reused.