JPH0363726A - Hierlarchy type branch history table - Google Patents

Abstract

PURPOSE:To suppress the deterioration of a branch performance caused by a delay of an instruction prefetch by providing a branch history table of a small capacity which can be operated at a high speed and a branch history table which is operated at a low speed but has a large capacity on the hierarchical structure. CONSTITUTION:The subject table is provided with first branch history table means 2, 3 which hold address information of a branch instruction and branch information containing a branch destination address corresponding to its branch instruction in accordance with execution history of the past branch instruction, and can execute an access at a high speed, and second branch history table means 6, 7 having a larger capacity than that of first branch history table means 2, 3. In the case it is detected by a first detecting means that address information of a prefetch instruction word is registered in first branch history table means 2, 3, the corresponding branch destination address is read out of first branch history table means 2, 3, and in the case it is detected by a second detecting means, the address is read out of second branch history table means 6, 7 corresponding thereto. In such a way, in the case of executing repeatedly the same branch instruction, the table can be operated at a high speed especially by utilizing the former.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This patent relates to high-speed processing of one branch instruction, and particularly to high-speed processing of branch instructions using a branch history table.

[Prior Art] Increasing the speed of branch instructions is an important problem in Neumann-type computers, and as a solution to this problem, a branch history table (1973--1983), which stores addresses of past branch instructions and branch destination addresses in pairs, has been proposed. No. 22384), and a branch decode table (US Pat. No. 4,477.8
No. 72).

[Problems to be Solved by the Invention] Among the conventional branch acceleration techniques described above, the single branch history table has an abnormally large number of single branch instruction classification degrees of about 25%, so it is necessary to store a large number of branch instructions. Therefore, it is often necessary to configure memory with a large capacity.

However, while today's logic circuits have become significantly faster, memories have not become so fast.

Therefore, when designing a high-speed computer, it is necessary to set the machine cycle to a small number, and the slow memory access time becomes a bottleneck.

This causes a problem in that the indexing of the branch history table is delayed and the performance of branch instructions is poor. In particular, when a branch instruction for a loop is always executed multiple times, it is necessary to index the branch history table as early as possible in order to improve the performance of the loop.

Accordingly, one object of the present invention is to provide a branch history table that can particularly speed up execution when the same branch instruction is repeatedly executed.

[Means for Solving the Problems] The hierarchical branch history table of the present invention corresponds to the address information of a branch instruction and the branch instruction according to the execution history of past branch instructions in a data processing device that prefetches instruction words. Holds branch information including branch destination address.

A first branch history table means that can be accessed at high speed stores branch information including address information of a branch instruction and a branch destination address corresponding to the branch instruction according to the execution history of past branch instructions. a second branch history table means having a larger capacity than the first branch history table means;
a first detecting means for detecting whether address information of an instruction word to be preempted in prefetching an instruction word is registered in the first branch history table means; 2nd branch to detect whether it is registered in the branch history table of 2nd branch history table.
If the detection means and the first detection means detect that address information of a preempted instruction word is registered in the first branch history table means, the corresponding branch destination address is stored in the first branch history table means. and means for reading the corresponding branch destination address from the second branch history table means when it is detected by the second detection means that it has been registered.

[Example] Next, one embodiment of the present invention will be explained with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. In FIG. 1, an instruction address register a1 is a register that receives a prefetched read address of an instruction word, receives an instruction word address output from an analog register converter (not shown) via a line 101, and receives an instruction word address output from a signal line 102. It is sent to the address comparison circuit a4 and the instruction address register b5 via the address comparison circuit a4 and the instruction address register b5.

Branch instruction address register 2 is a register that holds the instruction address for the most recent branch instruction, and sends the address via line 103 to address comparison circuit a4. This register is specially provided in the present invention,
The capacity is approximately 1 to 16 bits.

The branch destination address register 3 is a register that holds the branch destination address corresponding to the 9 branch instruction address register 2, and sends the address to the branch destination address selection circuit 11 via the line 104.

This is also specially provided in the present invention as described above, and its capacity is also the same as above.

The address comparison circuit a4 is a comparison circuit that compares the instruction prefetch address and the address of the branch instruction in the branch history table.
Compare the instruction fetch address inputted through 1 branch instruction address register 2 with the address of the branch instruction inputted through signal lines 10 and 3 from the 1 branch instruction address register 2, and check whether they match or not via the signal l1l105 to the priority control circuit. Send on 10. This is also specially provided in the present invention.

The instruction address register b5 is a register that holds an instruction fetch address for indexing a branch history table configured in memory, and receives the instruction prefetch address sent from the instruction address register a1 via the signal line 102, and A portion is sent as an address to the 1-branch instruction address array 6 and the branch destination address array 7 via the signal line 106.

The remainder is sent to the address comparison circuit b8 via the signal line 107.
Send to. Branch instruction address array 6 is a memory that stores addresses of one branch instruction.

A part of the instruction fetch address output from the instruction address register b5 via the signal line 106 is used as an address, and the branch instruction address is sent via the signal line 108 to the address comparison circuit b8. The capacity is about IK~2 bits.

Instruction destination address array 7 is 1-branch instruction address array 6
This is a memory that stores the branch destination address corresponding to the instruction address register b5, and uses a part of the instruction fetch address outputted from the instruction address register b5 via the signal line 106 as the address,
The branch destination address is sent to the branch destination address array register 9 via the signal line 109. This is also the same as above (
IK~2 bits.

The address comparison circuit b8, like the address comparison circuit a4, is a comparison circuit that compares the instruction pre-fetch read address with the address of the branch instruction in the branch history table. The fetch address is compared with the address of the branch instruction sent from the branch instruction address array 6 via the signal line 108, and the result is sent to the priority control circuit 10 via the signal line 110.
Send to.

The branch destination address array register 9 is a register that receives the predicted branch destination address, receives the branch destination address sent from the branch destination address array 7 via the signal line 109, and selects the branch destination address via the signal line 111. The signal is sent to the circuit 11.

The priority control circuit 10 selects the branch destination address held in the 1-branch destination address register 3 and the branch destination address array 7.
This is a circuit that controls which of the branch destination addresses held in is selected, and the matching information sent from the address comparison circuit a4 via the signal line 105 and the match information sent from the address comparison circuit b8 via the signal line 110. According to matching information.

A preliminary branch 1 branch destination address selection signal is sent to the branch destination address selection circuit 11 via the signal line 113.

A signal indicating that a predicted address has been detected is transmitted to the signal line 112.
to an instruction prefetch controller (not shown).

This is especially provided in the present invention.

The instruction destination address selection circuit 11 is a selection circuit that selects a predicted branch destination address. The predicted address to be sent is selected and sent via signal line 114 to the analog-to-digital converter. This is also specially provided in the present invention as described above.

Next, the operation of this example will be briefly explained.

Branch instruction address array 6 and branch destination address array 7
FIG. 2 shows a time chart in the case where an address is registered only in . The numbers in parentheses on the left side of the figure refer to the reference numerals of the apparatus of FIG. The operation in this case is the same as the conventional method.

When the instruction fetch address is held in the instruction address register a1 at T, the instruction address register b5 is held at the primary T2.
It will be retained. Here, instruction address register b5
The address of the branch instruction address array 6 is compared with the address of the branch instruction address array 6 by the address comparison circuit b8, and if they match, the predicted branch destination address is read out from the branch destination address array 7 to the branch destination address array register 9 at +T3. Therefore, the priority control circuit 10 causes the branch destination address selection circuit 11 to select this through the signal line 113.

Now, FIG. 3 shows the operation of the part added in the eight patents. In this case, the contents of the instruction address register a1 and the branch instruction address register 2 are directly compared by the address comparison circuit a4, and based on the result, the priority control circuit 10
3 causes the branch destination address selection circuit 11 to select the branch destination address register 3.

[Effects of the Invention] As explained above, the present invention has a hierarchical structure of a small-capacity branch history table that can operate at high speed and a large-capacity branch history table that operates at low speed.
Processing that takes at least 3T can be reduced to IT. As a result, when branching to the same address many times, such as in a short loop, by storing that address in a small-capacity branch history table that can operate at high speed, branch performance due to the delay in instruction prefetching is improved. can suppress the decline in

This is a diagram.

Explanation of symbols = 1...Instruction address register a, 2
... Branch instruction address register, 3... Branch destination address register, 4... Address comparison circuit a, 5...
Instruction address register b, 6... Branch instruction address array, 7... Branch destination address array, 8... Address comparison circuit, 9... Branch destination address array register.

10... Priority control circuit, 11... Branch destination address selection circuit.

[Brief explanation of drawings]

Figure 1 shows the configuration of an embodiment of the present invention, and Figures 2 and 3 show time charts of the embodiment. Knee (1) (5) (2) (4) Output (3) Fig. 3 T1T2 T3 T4 T5 I [ ■ 几4 Crow

Claims (1)

[Claims] 1. In a data processing device that prefetches instruction words, branch information including address information of a branch instruction and a branch destination address corresponding to the branch instruction is held according to the execution history of past branch instructions. a first branch history table means that can be accessed at high speed; and a first branch history table that stores branch information including address information of a branch instruction and a branch destination address corresponding to the branch instruction according to the execution history of past branch instructions. a second branch history table means having a larger capacity than the first branch history table means; a first detection means for detecting whether address information of an instruction word to be preempted in prefetching an instruction word is registered in the first branch history table means; a second detection means for detecting whether address information of the instruction word to be preempted in prefetching the instruction word is registered in the second branch history table means; If it is detected that the address information of the instruction word is registered, the corresponding branch destination address is read from the first branch history table means, and if it is detected by the second detection means that it is registered, the corresponding branch destination address is read out from the first branch history table means. A hierarchical branch history table characterized in that a branch destination address corresponding thereto is read from a second branch history table means.