JPH0480824A - Data processor - Google Patents

Abstract

PURPOSE:To prevent the estimation of undesired branch destinations and also to suppress the deterioration of performance due to the estimation of the undesired branch destinations by controlling the change of contents of a general-purpose register used for generation of addresses of the branch destinations. CONSTITUTION:When a branch instruction is registered into a branch history table 31, the Fxy shown by the lower rank bits of an instruction address register 2 are all set at '1'. When this instruction is taken out in the next time, the output of a branch instruction address comparator 9 is set at '1' since the coincidence is secured between the instruction extracting address of the register 2 and the output of a branch instruction address buffer 6. Under such conditions, the Fxy related to a register is reset to '0' as long as the contents of this register are previously changed. Thus the output of an AND circuit 10 is set at '0' and '1' when the Fxy selected by the No of a register No register 4 pointed by the instruction extracting address is equal to '0' and '1' respectively. These Fxy are set to a branch destination detection flag 11.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention is used for control when reading a branch history table in data processing. The present invention relates to a data processing device that uses the contents of a general-purpose register to generate a branch destination address and can improve performance by suppressing redundant branch destination prediction when reading a branch instruction.

[2] The present invention provides a branch history table that stores the address of a branch instruction and the branch destination address of this branch instruction as a pair;
In a data processing device equipped with a general-purpose register used for address modification, the content of the general-purpose register used to generate the address of the branch destination is managed, and output is prohibited when it is not suitable for prediction. This is designed to suppress performance degradation caused by prediction.

[Conventional technology]

The conventional branch history table was published in Tokuko Sho 50-22384.
As disclosed in US Pat. No. 70942, it is possible to predict the branch destination address based on the instruction fetch address at the time of instruction fetch, and it is possible to prefetch the branch destination instruction before processing the branch instruction. There is a method that speeds up the processing of branch instructions in this way. FIG. 5 shows its configuration.

[Problem to be solved by the invention]

However, when a general-purpose register is used to generate a branch destination address for a branch instruction, the branch instruction is intended to change the branch destination address based on the contents of the general-purpose register, so it is not necessary to store it in the branch history table. However, when the branch destination address changes, this is actually known when the branch instruction is being processed, so there is a possibility that subsequent processing will not be able to process it quickly, and that it will become slower due to penalties. be.

The present invention solves these problems, and aims to provide a device that can perform processing at high speed even if the branch destination address is changed.

[Means to solve the problem]

The present invention provides a data processing device that includes a branch history table that stores the address of a branch instruction and a branch destination address of this branch instruction as a pair, and a plurality of general-purpose registers that are used to modify the address. a first storage means for storing address generation information indicating whether or not the general-purpose register is used when generating a branch destination address corresponding to each entry in the table; and which general-purpose register is used when changing the contents of the general-purpose register; a second storage means for storing whether the change has been made; and the branch histogram); reading address generation information from the first storage means corresponding to the address of the branch instruction to be compared with the instruction fetch address stored in the IJ table; a register variable detection circuit including a reading means; a branch instruction address comparator for comparing an instruction fetch address with an address of a branch instruction stored in the branch history table when fetching an instruction; invalidating the comparison result indicated by the branch instruction address comparator when the second storage means indicates that the contents of the general-purpose register indicated by the address generation information have been changed; It is characterized by being equipped with a circuit.

The first storage means is a disk number buffer that stores the number of the general-purpose register used when generating the branch destination address of the branch instruction in correspondence with the branch history table, and the second storage means includes: The reading means includes a write register decoder and a change register decoder that manage register rewriting, and a plurality of flip-flops that manage changes in the contents corresponding to each encoder I-IJ and the general-purpose register. ) Corresponding when indexing the IJ child table) Multiple entry read selectors that output the change status of the contents of each of the general-purpose registers of the IJ, and changes to the general-purpose registers used to generate branch destination addresses when indexing the branch history table. It is preferable to include a register selector indicating whether or not there was a register selector.

[Effect]

When fetching an instruction, the instruction fetch address and branch history) I
Compare the address of the branch instruction stored in the J child table, and use this instruction fetch address to correspond to the address of the branch instruction stored in the branch history table being compared.
Read address generation information indicating whether a general-purpose register was used when generating a branch destination address. If this address generation information indicates that the general-purpose register has been changed, sending out the comparison result between the instruction fetch address and the address of the branch instruction stored in the branch history table is prohibited.

In this manner, by managing the changes in the contents of the general-purpose register used to generate the address of the branch destination, it is possible to suppress redundant prediction of the branch destination and to prevent the performance from decreasing due to the prediction.

Absolute excuse] Next, embodiments of the present invention will be described based on the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a register change detection circuit according to the embodiment of the present invention, and FIG. 3 is a block diagram showing the overall configuration of the embodiment of the present invention. It is a block diagram.

As shown in FIG. 3, the overall configuration according to the embodiment of the present invention includes an instruction fetch control circuit 32, an address generation circuit 33,
Main storage device 34, execution unit 35, branch history table 3
1, branch instruction address comparator 9, and AND circuit 10
Equipped with

Next, details of the configuration of the embodiment of the present invention will be explained with reference to FIGS. 1 and 2.

The embodiment of the present invention has a branch history (branch history) that stores the address of a branch instruction and the branch destination address of this branch instruction as a pair.
J child table 1, instruction address register (IAR) 2 used for address modification, branch destination address write register (DAVv'R) 3, and register number register (R
NR) 4, and predicted branch destination address register (PDA
R) 12 general-purpose registers, and as a feature of the present invention, address generation information indicating whether each of the general-purpose registers is used when generating a branch destination address is provided corresponding to each entry (IJ) of the branch history table 31. Register number buffer (RNB) 8 as a first storage means for storing
1, a write register decoder (WRD) 82, a change register decoder (URD) 83, and a plurality of A flip-flop 84 and a plurality of encoders as reading means for reading address generation information from the register number buffer (RNB) 81 in correspondence with the address of the branch instruction compared with the instruction fetch address stored in the branch history table 31).
IJ read selector (ERX) 85 and register selector (
Register variable detection circuit (RUCC) including RX) 86
8 is provided.

Write flag (WF) 1 is a flip-flop that indicates the operation of the branch history table.
WF) 1: “1” indicates registration; “0” indicates index. A write flag (WF) 1 receives a signal a sent from an instruction fetch control circuit (IFC) 32 via a signal line 101, and is connected to a branch instruction address buffer (TAB) 6 and a branch destination address buffer via a signal line 106. (D
AB) 7, register change detection circuit (RUCC) 8 and branch instruction address comparator (TAC) 9.

The instruction address register (IAR) 2 is a register for holding an instruction fetch address at the time of fetching an instruction or an instruction address of a branch instruction at the time of registering the branch history table of the branch instruction. Receives the command address sent from ADC) 33,
This instruction address is sent via signal line 107 to the branch instruction address buffer (TAB) 6 and branch instruction address comparator (TAC) 9, and the signal line 1
08 to the branch instruction address buffer (TAB) 6, branch destination address buffer (DAB)
7 and a register change detection circuit (RUCC) 8.

The branch destination address write register (DAWR) 3 is a register that holds the branch destination address when registering a branch instruction in the branch history table, and outputs the branch destination address sent from the address generation circuit (ADC) 33 as a signal. It is received via line 103 and sent to branch destination address buffer (DAB) 7 via signal line 109.

Register number register (RNR) 4 receives the general-purpose register number used when generating the branch destination address when registering the branch instruction +J table, and also receives the general-purpose register number when changing the contents of the general-purpose register. The register number sent from the execution unit 35 is sent to the register change detection circuit (RUCC) 8 via the signal line 110.

The register change flag (RUF) 5 is a flip-flop that lights up at the same time as the register number is received in the register number register (RNR) 4 when a general-purpose register is changed. The signal is sent to the register change detection circuit (RUCC) via the signal line 111.
)8.

The branch instruction address buffer (TAB) 6 is a memory that stores the address of a branch instruction in the branch history table, and when it is instructed to register from the write flag 1 via the signal line 106, it is stored in the instruction address register via the signal line 108. The instruction address information indicated by the upper bits of the instruction address register (IAR) 2 is stored in the address indicated by the lower bits of (IAR) 2 via the signal line 107, and the write flag (WF) 1 does not instruct registration. In this case, the command address information is read from the address indicated via the signal line 108 and sent to the read signal line 112.

The branch destination address buffer (D'AB) 7 is a memory that stores the branch destination address corresponding to the branch instruction address buffer (TAB>6), and is instructed to register from the write flag (WF) 1 via the signal line 106. If the branch destination address is indicated by the branch destination address write register (DAWR) 3 via the signal line 109, it is stored in the address indicated by the lower bits of the instruction address register (IAR) 2 via the signal line 108, and the write flag is set. 1 does not instruct registration, the branch destination address is read from the address indicated via the signal line 108 and sent to the predicted branch destination address register (PDAR) 12 via the signal line 113.

The register change detection circuit (RUCC) 8 is a feature of the present invention, and is connected to the signal lines 106, 108, 110, .
Information sent from the write flag 1, the lower bit of the instruction address register (IAR) 2, the register number register (RNR) 4, and the register change flag (RUF) 5 are received via the signal line 111, and a comparison permission signal is sent to the signal line 114. The signal is sent to the AND circuit 10 via.

The branch instruction address comparator (TAC) 9 is a circuit that compares the instruction fetch address with the branch instruction address stored in the branch history table. If it is “1”, “0” is sent to the signal line 115, and the write flag (
If the output of “vVF)1 is “0”, the signal line 107
The upper bit of the instruction address register (IAR) 2 sent out via the signal line 112 is compared with the instruction address information sent out from the branch instruction address buffer (TAB) 6 via the signal line 112, and if the result is equal, it is "1". If not “
0'' is sent to the AND circuit 10 via the signal line 115.

The AND circuit 10 is an AND circuit that performs a logical product on the index result obtained, and detects a register change via the signal line 114 with the comparison result sent from the branch instruction address comparator (TAC) 9 via the signal line 115. The logical product of the comparison permission signals sent from the circuit (RUCC) g is taken, and the result is used as a detection signal to send the branch destination detection flag (
DHF) 11.

The branch destination detection flag (DHF) 11 is a flag indicating that a 2-prediction branch destination address has been detected, and the signal line 116
The detection signal sent from the AND circuit 10 is sent to the instruction fetch control circuit (IFC) 32 via a signal line 117.

The predicted branch destination address register (PDAR) 12 is a register that receives the predicted branch destination address in synchronization with the branch destination detection flag (DHF) 11, and is sent from the branch destination address buffer (DAB) 7 via the signal line 113. It receives the branch destination address and sends it to the address generation circuit (ADC) 33 via the signal line 118.

FIG. 2 is a block diagram showing the configuration of the register variable detection circuit in the embodiment of the present invention. Register number buffer (
RNB) 81 is a branch instruction address buffer (TAB)
6. Branch destination address buffer (DAB) This is a memory that stores the number of the general-purpose register used when generating the branch destination address of a branch instruction, corresponding to 7. Registration is instructed by write flag (WF) 1 via signal line 106. When the write flag 1 is set, the register number indicated by the register number register (RNR) 4 is stored via the signal line 110 at the address indicated by the lower bits of the instruction address register (IAR) 2 via the signal line 108, and the write flag 1 is set. If registration is not indicated, read the stored register number from the same address and send it to the register selector (RX) via the signal line 801.
)86.

A write register decoder (WRD) 82 is a decoder for managing rewriting of register contents, and is a decoder for managing rewriting of register contents.
When registration is instructed by write flag (WF) 1 via signal line 108, the instruction address register (
The lower bits of IAR)2 are decoded and only the corresponding output lines 802.803.804 are set to "1", and if the write flag (W F )1 does not indicate registration, all output lines 802.802. 803,-,. 804 is “
0". Also, the output lines 802, 803, 80
4 is each flag FooF+.

F mQ, FIIFI+""'Fml+ ""'F
OIFlh""' is connected to F+att, and n is branch instruction address buffer (TAB) 6, branch destination address buffer (DAB) 7, register number buffer (RNB) 8
For one entry, there are as many m as there are registers.

The change register decoder (URD) 83, like the write register decoder (WRD) 82, is a decoder for managing the rewriting of register contents. If indicated, only the output lines 805, 806 and 807 corresponding to the register number indicated by the register number register (RNR) 4 via the signal line 110 are set to “1”.
If no change is indicated, all output lines are set to "0". Output lines 805, 806 and 807 are respectively FooFa+FOR+FI OFI+
""' F l n+ ""' F IROF ff1
l l""' F mn.

Flag (F, y) (x = 0-m5Y = (L
-n) 84 is a flip-flop (F/F) for managing changes in general-purpose register contents corresponding to each entry (y) and each general-purpose register (X); 0, the write register decoder (WR
D) Registration for entries newer than 82 is indicated (
It is set to "1" and held, and is sent to the change register decoder (URD) via the output line 805.
) 83 indicates that the corresponding general-purpose register has been changed, it is reset to "0"'. Further, the output is outputted to an entry read selector (ERX) 85 corresponding to each general-purpose register.

The IJ read selector (ERX) 85 is a selector for outputting the change status of the contents of each general-purpose register of the corresponding entry when indexing the IJ table.
FIIY (X=0・m, y=On) for each general-purpose register
), selects the output of the entry indicated by the lower bit of the instruction address register (IAR) 2 via the signal line 108, and outputs it to the register selector (RX) 86.

The register selector (RX) 86 is a selector that indicates whether or not there has been a change in the general-purpose register used to generate a branch destination address when indexing the branch history table, and receives the output of each entry read selector (ERX) 85. , register number buffer (RNB) 811 via signal line 801
It is selected based on the general-purpose register number indicated by and outputted to the AND circuit IO via the signal line 114.

Next, the operation of the embodiment of the present invention will be explained.

FIG. 4 is a flowchart showing the operation flow of the embodiment of the present invention.

If the branch instruction corresponding to 1 is not yet registered in the branch history table, the instruction address register (IAR) 2
Even if the instruction fetch address is set in
C) The output of 9 (output to signal line 115) becomes "O", and the output of AND circuit 10 (output to signal line 116) also becomes "
0'' and the branch destination detection flag (DHF) 11 does not light up.

When registering a branch instruction in the branch history table 31,
At the same time that write flag (WF) 1 lights up (becomes "1"), the instruction address of the branch instruction is written to instruction address register (IAR) 2, the branch destination address is written to branch destination address write register (DAWR) 3, and the branch destination address is written to instruction address register (IAR) 2. The general register number used to generate the address is the register number register (R
NR) is set to 4. Write flag (WF) 1 is “
1”, the branch instruction address buffer (T
AB) 6 instruction address register (IAR) The address indicated by the lower bit of 2 is the instruction address register (IAR).
The upper bit of AR) 2 is the branch destination address buffer (D
AB) 7 contains a branch destination address write register (DA
The contents of WR) 3 are the register number buffer (RNB) 81
The register number indicated by the register number register (RNR) 4 is written into , and at the same time, F xy indicated by the lower bits of the instruction address register (IAR) 2 are all set to "1".

The next time you retrieve an instruction, use the instruction address register (I
Since the instruction fetch address of AR) 2 and the output of the branch instruction address buffer (TAB) 6 match, the output of the branch instruction address comparator (TAC) 9 becomes "1'". At this time, if the contents of the register have been changed before then, the F)ly associated with that register is reset to "0".
It has become.

As a result, if Flly selected by the register number of the register number register (RNR) 4 indicated by this instruction fetch address is "0", the output of the AAND circuit 10 is "0" and FMy is "1". If so, it becomes "1" and is set in the branch destination detection flag (DHF) 11.

[Effect of Hathu]

As explained above, according to the present invention, by managing changes in the contents of general-purpose registers used to generate branch destination addresses, redundant prediction of branch destinations is suppressed, and performance degradation caused by this is suppressed. There is an effect that can be done.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a block diagram showing the configuration of a register change detection circuit according to an embodiment of the present invention. FIG. 3 is a block diagram showing the overall configuration according to an embodiment of the present invention. FIG. 4 is a flowchart showing the operation flow of the embodiment of the present invention. FIG. 5 is a block diagram showing a conventional configuration. 1...Write flag (WF), 2...Instruction address register (IAR), 3...Branch destination address write register (DAWR), 4...Register number register (RNR), 5...Register Change flag (R
UF) 6...Branch instruction address buffer (TAB)
,? ...Branch destination address buffer (DAB),
・Register change detection circuit (RUCC), 9... Branch instruction address comparator (TAC), 10... AND circuit, 11... Branch destination detection flag (DHF), 12.
...Predicted branch destination address register (PDAR), 3
1... Branch history table, 32... Instruction fetch control circuit (IFC), 33... Address generation circuit (A
DC), 34... Main storage device, 35... Execution unit,
81...Register number buffer (RNB) 82...
Write register decoder (WR'D), 83... Change register decoder (URD), 84... Flip-flop, 85... Entry read selector (ERX)
, 86...Register selector (RX).

Claims (1)

[Claims] 1. In a data processing device comprising a branch history table that stores the address of a branch instruction and the branch destination address of this branch instruction in pairs, and a plurality of general-purpose registers used for modifying addresses. , a first storage means for storing address generation information indicating whether or not the general-purpose register was used when generating a branch destination address corresponding to each entry of the branch history table; a second storage means for storing which general-purpose register has been changed; and address generation information from the first storage means corresponding to the address of the branch instruction to be compared with the instruction fetch address stored in the branch history table. a register variable detection circuit including a readout means for reading, a branch instruction address comparator for comparing an instruction fetch address with an address of a branch instruction stored in the branch history table when fetching an instruction; invalidating the comparison result indicated by the branch instruction address comparator when the second storage means indicates that the content of the general-purpose register indicated by the address generation information has been changed; A data processing device characterized by comprising a circuit for: 2. The first storage means is a register number buffer that stores the number of the general-purpose register used when generating the branch destination address of the branch instruction in correspondence with the branch history table, and the second storage means is a register number buffer that stores the number of the general-purpose register used when generating the branch destination address of the branch instruction. 2. The data processing device according to claim 1, further comprising a write register decoder and a change register decoder for managing rewriting of the general-purpose register, and a plurality of flip-flops for managing changes in contents corresponding to each entry and the general-purpose register. 3. The reading means includes a plurality of entry read selectors that output the change status of the contents of each general-purpose register of the corresponding entry when indexing the branch history table, and a plurality of entry read selectors used to generate a branch destination address when indexing the branch history table. 2. The data processing apparatus according to claim 1, further comprising a register selector that indicates whether or not there has been a change in the general-purpose register.