JPH06230963A - Memory access controller - Google Patents

Abstract

PURPOSE:To speed up program processing while adjusting conflict relation by comparing the memory address of an instruction during its execution. CONSTITUTION:Plural instructions are read out of a program and held temporarily in an instruction buffer part 7. At this state, an address calculation part 8 calculates the addresses of the respective instructions, which are stored in a memory access buffer part 12 while their memory addresses are made to correspond to one another. An address comparison part 14 compares the memory addresses of the respective instructions stored in the memory access buffer part 12 to judge the conflict relation. When memory addresses conflict with each other, control for execution from an instruction which is read out first is performed according to the sequence relation of the instructions displayed at the memory access buffer part 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access control device used when a plurality of instructions read from a program are executed in an unordered order from the executable one to increase the operation speed.

[0002]

2. Description of the Related Art A program executed by an information processing device is
It is usually constructed by arranging many instructions. Generally, when executing a program, the instructions are read in order from the beginning and the instructions are executed in the order in which they are called. However,
This cannot sufficiently increase the processing speed. Therefore,
A method has been introduced in which a plurality of instructions are read from a program one after another, an executable instruction among these instructions is detected, the instructions are executed in random order unless conflict occurs, and the utilization efficiency of a computing unit is improved ( Mike Johnson “Superscalar
Microprocessor Architecture ”Prentice Hall 199
0). In order to realize this method, it is necessary to solve the memory address conflict due to the memory access instruction.
The method is introduced in the following documents, for example.
(A) "Load / Store Pipeline of DSN Superscalar Processor Prototype" IPSJ Computer Architecture Research Group 86-4

LAS is a memory address conflict.
(Load after store), SAL (store after load),
There are three types of SAS (store after store). When there is such a dependency among a plurality of memory access instructions, it is necessary to detect this and always consider a measure to execute the instruction read first. Therefore, it is necessary to compare in advance the memory address of the memory access instruction to be executed with the memory addresses of all the previously read memory access instructions that have not yet been executed.

FIG. 2 is a diagram for explaining the operation of the memory access instruction. As shown in the figure, program 1 has instructions C1 and C
It is assumed that each instruction is read from top to bottom, such as 2 ... C5. At this time, if the instructions C1, C3 and C4 are memory access instructions, for example, the instruction C1 accesses the memory address A1 and the instruction C3 accesses the memory address A2. The instruction C4 also accesses the memory address A2. In this case, the execution of the instruction C3 prior to the instruction C1 does not affect the processing by the instruction C1. However, if the instruction C4 is executed before the instruction C3, the same memory address A2 is accessed, so that if the contents are rewritten, the execution result becomes inconsistent.
Therefore, it is necessary to determine whether the memory addresses of the instruction C3 and the instruction C4 are the same, and if they are the same, the control of causing the instruction C3 to precede the instruction C4 without fail.

However, such a memory address is not known only by decoding the instruction. FIG. 3 shows a memory address generation timing explanatory diagram. This figure is
It shows a process in which the instruction C3 and the instruction C4 are executed and a memory address is generated. Timings T1, T2, T
It is assumed that time elapses, such as 3 and T4.
As shown in the figure, the instruction C3 is fetched at the timing T1 and is decoded at the timing T2. At this stage, the memory address is not known yet. After that, at timing T3, address calculation is performed when the instruction is executed. At this time, the memory address A2 is known.
The instruction C4 is processed at the same timing,
At timing T3, memory addresses are generated and their contents are compared. Therefore, at this stage, a memory address conflict is found and the instruction C3 is executed first.

In pipeline processing, the processing of one instruction precedes the other by one machine cycle. Therefore, in order to perform the above-described processing, it is necessary to hold the memory address at the stage when the address calculation of one instruction is completed, and to clarify the read order relationship of each instruction. Since it is not easy to perform such processing at the time of executing a program, conventionally, for example, information for designating an execution order is added to an instruction at the time of compilation. Generally, memory access instructions are classified into the following three types. First, the instruction "strongly Ordered" is an instruction that should be executed in the order of instructions. When it is clear that a competitive relationship exists or when it cannot be determined that this competitive relationship exists, this instruction is executed in the order of reading. Also, "weakly O
The instruction "rdered" is an instruction that ensures that memory access instructions of the same data type are executed in order. Therefore, it does not apply between memory access instructions for different data types. The instruction "Unordered" is an instruction that can be executed without following the reading order at all. This applies when it can be concluded that each instruction has no mutually dependent competitive relationship. Therefore, such instructions are executed in any order, and high-speed arithmetic processing is possible.

[0007]

By the way, in the prior art as described above, the instruction order is set before the execution of the arithmetic processing. Therefore, if there is an order relation that cannot be judged before execution, consider the case where a conflict occurs and
Settings are made so that the instructions are executed in the order of reading. Therefore, even if it is found that there is no competition between instructions at the stage of actually executing the program, these instructions are executed in the order of reading, so that the processing speed of the program cannot be sufficiently increased. was there. Furthermore, there is a possibility that a situation may occur in which it is determined in advance that a conflict relationship does not occur, and an instruction that can be executed without following the instruction order causes a dependency relationship during execution, resulting in an error in the operation processing result. . In addition, in order to carry out the above-mentioned treatment, a new bit is added to each instruction in advance to add information indicating the type of the instruction. Therefore, there is also a problem to be solved that the capacity of the memory for storing the entire program becomes large. The present invention has been made in view of the above points, and it is an object of the present invention to provide a memory access control device that speeds up program processing while comparing memory addresses of instructions during execution and adjusting a competition relationship. It is what

[0008]

A memory access control apparatus according to the present invention accesses an instruction buffer unit for reading and holding a plurality of instructions read from a program before execution, and a memory access instruction in the instruction buffer unit. An address calculation unit that calculates a target memory address, a memory access buffer unit that displays the execution order of each memory access instruction in the instruction buffer unit and the memory address and data of each instruction, and a memory address of each instruction An address comparison unit for comparing and a memory access control unit that prioritizes execution of the previously read instruction by referring to the memory access buffer unit when there is a conflicting instruction with a matching memory address It is characterized by.

[0009]

This device reads a plurality of instructions from the program and temporarily holds them in the instruction buffer section. At this stage, the address calculation unit executes the address calculation of each instruction, and the instruction and the memory address of the instruction are associated with each other and stored in the memory access buffer unit. The address comparison unit compares the memory address of each instruction stored in the memory access buffer unit and determines the competition relationship. When the memory addresses conflict, the instruction read first is executed according to the order relation of the instructions displayed in the memory access buffer section. Therefore, the memory address conflict of the memory access instruction is always determined at the time of execution, and the instruction determined to have no conflict at that stage is executed out of order, so that the processing speed can be maximized. Moreover, it is not necessary to add information indicating the execution order to the instruction in advance.

[0010]

The present invention will be described in detail below with reference to the embodiments shown in the drawings. FIG. 1 is a block diagram showing an embodiment of a memory access control device of the present invention. The device shown in the figure is a device for reading out each instruction constituting a program stored in the instruction cache 5 and executing the processing by accessing the memory 6 or the like. An instruction buffer unit 7 is provided to store the instructions read from the instruction cache 5. In addition to this, an address calculation unit 8, a register file 9, a memory access instruction control unit 10 and the like are provided. The memory access instruction control unit 10 includes
A memory access instruction decoding unit 11, a memory access buffer unit 12, an instruction number control unit 13, and an address comparison unit 14 are provided. Further, between the memory access instruction control unit 10 and the memory 6, the memory access control unit 1
5 are provided.

The instruction cache 5 comprises a conventionally well-known cache memory for transferring and storing a part of a program in order to speed up the program execution. The instruction buffer unit 7 is newly provided in the present invention, and is composed of a storage unit for reading and holding a plurality of memory access instructions from the instruction cache 5 before executing them. The instruction buffer unit 7 is composed of an instruction unit 7-1 and a number unit 7-2. The instruction unit 7-1 stores the read instruction, and the number unit 7-2
A number for identifying each instruction is stored in. This number is a code provided for associating a memory address or the like stored in the memory access buffer unit 12 with a memory access instruction of the instructions stored in the instruction buffer unit 7.

The address calculation unit 8 is an arithmetic processing unit for decoding each instruction stored in the instruction buffer unit 7 and calculating the address when the instruction is a memory access instruction. The register file 9 is composed of a data memory that stores data necessary for the address calculation and the like. The memory access instruction decoding unit 11 of the memory access instruction control unit 10 is a circuit for decoding each instruction read from the instruction cache 5. This circuit identifies the instruction as a memory access instruction. The memory access buffer unit 12 stores a memory access table 21 shown in FIG. 5, which will be described later, and is composed of a storage area that holds information about the memory address of each instruction. In order to associate the memory access table 21 provided in the memory access buffer unit 12 with each instruction stored in the instruction buffer unit 7,
The instruction number control unit 13 is provided, and the instruction number queue 22 is stored therein.

FIG. 4 is an explanatory diagram of the instruction number queue. This instruction number queue has number values for identifying each instruction by the number of instructions that can be stored in the instruction buffer unit 7. Here, for example, the number is set to "8", and the number values "1" to "8" are prepared. Then, a Val field is added to each field for storing the number value so as to indicate whether or not the number value is valid. That is, when the Val field is “1”, the number value is valid, and the number value can be added to the memory access instruction newly stored in the instruction buffer unit 7.

FIG. 5 is an explanatory diagram of the memory access table. This memory access table has an instruction number field, an instruction field, a memory address field,
It is composed of a register name field, a data field and a Val field. In the instruction number field, the number added to the instruction stored in the instruction buffer unit 7 is entered. That is, for example, the Val fields of the instruction number queues are all "1" in advance, and when one instruction is stored in the instruction buffer unit 7, the Val field of the number value 1 of the instruction number queue is "0". "It becomes. Then, the number value is stored in the number portion of the instruction buffer unit 7, and at the same time, the number value is stored in the uppermost stage of the memory access table 21. As a result, the instruction stored in the instruction buffer unit 7 and the information stored in the memory access table 21 are associated with each other.

The instruction field of the memory access table 21 stores the type of instruction stored in the instruction buffer unit 7. In the embodiment, only the memory access instruction is stored in the instruction buffer unit 7. Then, the instruction is classified into, for example, a STORE instruction and a LOAD instruction. Therefore, display data of either STORE or LOAD is stored in the command field. The memory address field stores a memory address to be accessed by the instruction. This memory address is data obtained by arithmetic processing by the address calculator 8 described above. The register name field stores a register number that temporarily holds data used when performing STORE or LOAD.
The data used for the LOAD or STORE is stored in the data field. In the Val field, a value indicating whether the contents of each row of the table are valid is stored. When it is valid, it is "1", and when it is invalid, it is "0".

Hereinafter, an example of the operation of the device of the present invention will be specifically described in order. FIG. 6 is a memory access instruction operation timing chart. For example, assume that two memory access instructions are read from the instruction cache 5 of the device shown in FIG. 1 and held in the instruction buffer unit 7. This command has the content as shown in FIGS. 6 (a) and 6 (b).
One is a STORE instruction and the other is a LOAD instruction. The first argument is indicated as R2 and R3, respectively, and these are register numbers for holding data at the time of instruction execution. Also, the second argument is displayed as R10 and R11, which indicate the address register numbers for memory access. Further, this apparatus executes pipeline processing. As shown in FIG. 6, in processing of each instruction, f is fetch, d is decode, and e is
m is memory access and w is register writing 5
It consists of different stages.

Before the execution of the program, all the values of the Val field of the instruction number queue shown in FIG. 4 are "1", and the values of all the Val fields of the memory access table shown in FIG. 5 are all "0". Has become. Here, at timing T1, the STORE instruction is fetched from the instruction cache 5 into the instruction buffer unit 7. At this time,
The memory access instruction decoding unit 11 shown in FIG.
Recognize that the read instruction is a memory access instruction. In this case, the STORE instruction is stored in the instruction section 7-1 of the instruction buffer section 7. Then, the instruction number control unit 13 invalidates the Val field of the first number value 1 of the instruction number queue, that is, switches it to the value “0”, and sets the number value “1” to the number unit 7- of the instruction buffer unit 7. Store in 2. In addition, the memory access buffer unit 12 stores the same number value in the instruction number field of the memory access table 21, and at the same time Val
The field is enabled, that is, switched to "1".

At the next timing T2, the timing T1
The STORE instruction fetched in (1) is decoded in detail, and the memory address for address calculation is read from the register number R10. This register is provided in the register file 9 shown in FIG. At this time,
For example, it is assumed that the data to be stored is read from the register of the register number R2, but it cannot be read due to the register data hazard. The register data hazard means a state in which the register with the register number R2 is occupied by another instruction or the like and cannot be used by another instruction. At this stage, the register name is written in the register name field of the memory access table 21. Note that such a register data hazard state is assumed to continue until the end of timing T4, for example.

On the other hand, at timing T2, LOAD
The instruction is fetched from the instruction cache 5 and decoded by the memory access instruction decoding unit 11. Also in this case, at the timing T3, the S executed earlier is executed.
Similar to the TORE instruction, that instruction is stored in the instruction buffer unit 7, the number value 2 is fetched from the instruction number queue, and the number is stored in the number unit 7-2. The number value is stored in the instruction number field of the memory access table 21 shown in FIG. 5, and the Val field becomes valid.
At the timing T3, the address of the STORE instruction is calculated, but the LOAD instruction is decoded at this timing, and the register name R3 for executing the LOAD instruction is written in the register name field in the memory access table 21. Be done.

At timing T4, the memory access of the STORE instruction is supposed to be performed. However, the register number R that holds the data to be stored
Since the second register cannot be read, the memory access stage cannot proceed. At timing T5,
It becomes possible to read the register of the register number R2 by the STORE instruction. Therefore, the data stored in this register is written in the data field of the memory access table 21, and the instruction with the corresponding number value 1 is fetched from the instruction buffer unit 7. As a result of moving the necessary data to the memory access table by the STORE instruction, it is no longer necessary to store the STORE instruction in the instruction buffer unit 7, so that the next memory access instruction can be protected.

With this LOAD instruction, memory access is possible prior to the STORE instruction if there is no address conflict. Therefore, the address comparison unit 14 compares the memory address of the STORE instruction with the memory address of the LOAD instruction. That is, at timing T3, STORE
The memory address of the instruction is calculated, and at timing T4, the memory address of the LOAD instruction is calculated by the address calculation unit 8
Competitive judgment is made by comparing and comparing both. In the case of this embodiment, the memory addresses do not match as shown in the memory address field of the memory access table 21 shown in FIG.
The D command can be processed in advance. Therefore, the memory access instruction control unit 10 notifies the memory access control unit 15 that the memory access of the LOAD instruction is performed.

On the other hand, if the address comparison unit 14
If it is determined that the memory addresses of the STORE instruction and the LOAD instruction match, the STOR read previously
The E instruction is executed first. In this example, it is set in advance that the instruction read out before the lower stage is always stored in the upper stage of the memory access table. Therefore, when the information that the memory addresses match is output from the address comparison unit 14, the Val field in the upper stage of the memory access table is automatically set to the valid S.
The memory access control unit 15 is notified so that the TORE instruction is processed first. By adopting such a configuration, the address comparison unit 14 does not need to process the instruction read order relationship.

At timing T6, memory access is executed by the STORE instruction. Also, the data obtained by the LOAD instruction at the same timing is the register name R
3 register. In the case of the LOAD instruction, the data read from the memory 6 is temporarily stored in the data field of the memory access table 21. This is written in the register with the register name R3 at timing T6. Then, at this time, the LOAD instruction with the number value of 2 in the instruction buffer unit 7 is taken out, and the Val field corresponding to the LOAD instruction in the memory access table 21 is invalidated, that is, is set to “0”. In this way, the information for the LOAD instruction is deleted from the memory access table 21, and at the next timing T7, the stage of writing to the register by the STORE instruction ends. here,
For the STORE instruction, V of the memory access table
The al field is invalid. When the execution of the instruction is completed, the instruction number control unit 13 writes the number value “2” in the uppermost portion of the instruction queue 22 where the Val field is “0”, and sets the Val field to “1”. Allows the use of:

As described above, the device of the present invention generally operates on the following principle. FIG. 7 shows an operation flowchart of the device of the present invention. In the figure, step S1
The instruction is fetched from the instruction buffer unit 7. And
In step S2, address calculation is performed. In step S3, the memory access table 21 is referred to, and in step S4, it is determined whether or not there is a conflicting instruction at the upper level of the table. If there is no conflicting instruction, the process proceeds to step S6 and the instruction is executed. If there is a conflicting instruction, in step S5, it waits until the Val flag of the higher-order conflicting instruction of the memory access table 21 becomes invalid. That is, the memory access is always executed sequentially from the higher order instruction in the memory access table.

The present invention is not limited to the above embodiments. The configuration of the memory access table for memory address conflict control is not limited to the above example, and at least the instruction and its memory address are associated with each other, and the read order relationship of each instruction is clear. It can be anything. Further, in the above embodiment, the instruction buffer unit and the memory access table are controlled by the instruction number control unit so that the instruction number having the same number value is assigned, but if the instruction buffer unit can store the memory access table at the same time. With such a configuration, it is not necessary to take the above means.

[0026]

The memory access control device of the present invention described above reads and holds a plurality of memory access instructions read from a program in the instruction buffer unit before execution, and the address calculation unit stores each instruction. The memory address to be accessed is calculated, the reading order of each instruction in the memory buffer and the access address of the instruction are displayed in the memory access buffer section, and the access address of each instruction is compared in the address comparison section When there is a conflicting conflicting instruction, the instruction read out first is prioritized so that it is controlled so that it is not necessary to add information indicating the execution order to each instruction in advance. Are executed in the order in which they are read, otherwise the instructions are executed in any order. It is possible, can be efficiently performed very fast program execution.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a memory access control device of the present invention.

FIG. 2 is an operation explanatory diagram of a memory access instruction.

FIG. 3 is an explanatory diagram of memory address generation timing.

FIG. 4 is an explanatory diagram of an instruction number queue.

FIG. 5 is an explanatory diagram of a memory access table.

FIG. 6 is a memory access instruction operation timing chart.

FIG. 7 is an operation flowchart of the device of the present invention.

[Explanation of symbols]

 5 instruction cache 6 memory 7 instruction buffer unit 8 address calculation unit 10 memory access instruction control unit 12 memory access buffer unit 13 instruction number control unit 14 address comparison unit 15 memory access control unit

Claims (1)

[Claims] 1. An instruction buffer unit for reading and retaining a plurality of instructions read from a program before execution, an address calculation unit for calculating a memory address to be accessed by a memory access instruction in the instruction buffer unit, A memory access buffer unit that displays the execution order of each memory access instruction in the instruction buffer unit and the memory address and data of each instruction; an address comparison unit that compares the memory address of each instruction; A memory access control unit comprising a memory access control unit that prioritizes execution of a previously read instruction when there is an instruction, by referring to the memory access buffer unit.