JPH01280851A - Cache store control system - Google Patents

Abstract

PURPOSE:To realize a high-speed storing action by performing a tag searching action of a cache memory based on a store address before production of write data and writing the data in the cache memory when the write data is produced. CONSTITUTION:An address register 2 is prepared to hold a cache access address together with a store address register 10 which holds an address when a cache is stored, a deciding circuit 12 which decides the validity of said store address, and a data register 15 which holds the write data to be written in a cache memory 1. Then a tag searching action is carried out to the memory 1 based on the store address before production of the write data. The data are written in the memory 1 before production of the write data. Thus a high-speed storing action is ensured.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is a cache store control method for improving the performance of a computer having a cache memory. [Prior Art] Fig. 3 shows a conventional cache - It is a block diagram showing a store control method.

In the figure, 1 is a cache memory, which includes an index section and a status section.

It has a data section, a tag section, etc. 2 is an address register, 3 is a hold circuit that holds an address, 4 is a hit detection circuit for determining the result of tag search, 5 is a priority determination circuit that determines the priority of a cache access request, 6 is a write control circuit that determines the cache access request that has been given priority by the priority determination circuit S together with the detection result of the hit detection circuit 4, and performs writing if the cache access request is in a store-enabled state. 7 is a cache access request bus, 8
is the address bus, and 9 is the write data bus.

Next, the operation will be explained.

In the store operation, first, cache access address information transferred through the address bus 8 is set in the address register 2, and then the address is held by the hold circuit 3 until the write operation is completed.

Next, the tag section of the cache memory 1 is read using that address, and the hit detection circuit 4 determines whether there is a cache hit or not (cache miss). At this time, if a cache miss occurs, the block is usually
A detailed explanation of whether a load request is output to set the cache hit state or a cache miss is well known is omitted here.

Next, in parallel with the cache hit detection described above, the priority determination circuit 5 determines the requests that have already been transferred by the cache access request bus 7, and if the cache store request has priority, the write is performed. The control circuit 6 becomes significant (valid) and the write data/
Write data transferred on bus 9 is written to the data portion of cache memory 1 indicated by address register 2.

(Problem to be Solved by the Invention) Since the conventional cache store control method is configured as described above, it is necessary to obtain an address and write data before issuing a cache store request. After a cache hit is issued, two consecutive memory accesses are required: a tag read operation to determine a cache hit, and a cache data write operation after a hit is detected, and the store operation is faster than a cache read. The problem was that it could not be done at high speed.

This invention was made in order to solve the above-mentioned problems, and it is possible to send a cache store request to a store where write data is prepared.
Maintains store address and cache hit state,
The purpose of the present invention is to obtain a cache store control method that can store write data at high speed without performing another tag search when it is prepared, and can perform a high-speed store operation.

[Means to solve the problem]

A cache store control method according to the present invention is a cache store control method for a computer having a cache memory. It includes an address register, a determination circuit that determines the validity of the store address, and a data register that holds write data to the cache memory.
Performs a cache memory tag search according to the address and stores the data in the cache before writing data is generated.
It is configured to be written into memory.

(Operation) In the cache store control method of the present invention, a cache memory tag search is performed according to the address at the time of cache store before writing data is generated, so that tag search is not performed when writing data is generated. Data can be written to cache memory. That is, a cache hit can be detected during the tag search, and therefore a store operation can be performed at high speed.

(Example) Hereinafter, one embodiment of the present invention will be described based on the drawings.

FIG. 1 is a block diagram showing a cache store control system for a computer according to the present invention, and the same components as those in the conventional FIG. 3 will be described with the same reference numerals. In the figure, 1 is a cache memory provided in the computer, 2 is an address register that holds a cache access address, 4 is a hit detection circuit for determining the result of tag search, and 5 is a priority determination circuit. , 6 is a write control circuit, 7
8 is the cache access request bus, 8 is the address bus, 9 is the write data bus, and 10 is the store address bus that holds the address when storing the cache.
11 is an address selection circuit; 12 is a cache store 18 validity determination circuit that determines the validity of the store address; 13 is a store pending request flag; 14 is a store address valid flag; 15 is a register; a write data buffer register that holds old data to be written into cache memory 1; 16 is a write bus selection circuit;
17 is a read data bus.

Next, the operation will be explained.

Cache store requests sent by cache access request bus 7 have priority f
When priority is obtained by the IT-specific circuit 5, the address register 2 is selected by the address selection circuit 11, a tag search is performed, and the result is sent to the hit detection circuit 4 and the cache.
The store validity determination circuit 12 determines. At this time, if the address is valid, the store address valid flag 14 is set, and the store pending request flag 13 is also set.

Thereafter, other cache access requests can be executed under the control of the priority determination circuit 5 until the write data is sent to the write data bus 9.

Next, when write data is generated, the data is sent to the old data bus 9, and at the same time, an 8-pack data enable signal is sent to the cache access request bus 7, and the priority determination circuit 5 sends the data to the old data bus 9. Other cache/
If there is no access, the store pending request gets priority, and if the store address valid flag 14 is set at this time, it is considered a cache hit and the store request is not accessed.
The address register 10 is selected and the data on the old data bus 9 is written directly into the data section of the cache memory 1. If priority cannot be obtained at this time, the data is written to the write data buffer register 15 and held, and at the same time, the store pending request flag is set to 1.
Raise the priority of 3 and wait until you get priority.

When the above priority is obtained, the store address valid flag 14 is checked again, and if it is valid, the store address is
The data in the write data buffer register 15 is selected by the write path selection circuit 16 to the data portion of the cache memory 1 indicated by the register 10, and the data in the cache memory 1 is
Complete the store operation.

FIG. 2 shows the control of the cache memory 1, arithmetic control, and data flow. In the figure, 18
21 indicate simple components of the arithmetic execution unit to which the write data bus 9 and read data bus 17 in FIG. 1 are connected, 18 is a data register, 19 is an input selection circuit for the data register 18, 20 is an adder, and 21 is an accumulator.

Here, in order to make the flow of address data easier to understand, the same components are arranged for each machine cycle (N-N+3). Furthermore, for convenience of explanation, the cache memory control section and the arithmetic control section are connected one cycle after another.

Next, the operation will be explained for each cycle.

(B) Cycle (N) is Fetch
- The case where request (A) is being executed is shown.

At this time, the fetch address (
A) is set, and a cache read is performed via the address selection circuit 1. Further, the read data hit by the cache is sent to the read data bus 17.

(b) In cycle (N+1), store request (
B) is executed.

At this time, address register 2 contains the store address (
B) is loaded, a tag search is performed via the address selection circuit 11, and the hit detection circuit 4 determines whether or not the store has been hit.

At the same time, the arithmetic control section executes calculation of write data, and write data (Y) is generated in the accumulator 21.

(c) In cycle (N+2), the fetch request (C) is executed and write data (Y) is sent to the write data bus 9.

At this time, if a cache hit is detected in cycle (N+1), the store address (B) is transferred to the store address register 10 and the store address valid flag 14 is set. At the same time, the store pending request flag 13 is set.

This example shows a case where there is a conflict between the fetch request (C) and the store pending request generated above, but the fetch request (C) has priority.

At this time, since write data (Y) has been sent to the old write data bus 9, that data is loaded into the write data buffer register 15 and the priority of the store pending request is raised. In addition, cache memory 1 is
It is accessed by the fetch address (C) in the address register 2, and its read data (Z) is sent to the read data bus 17.

(d) In cycle (N+3), there is no cache access request from outside, so cycle (N+2
) Store pending quests or priority rights generated by
Ru. Then, the address selection circuit 11 selects the store address register 10, and since it is determined by the store address valid flag 14 whether there will be a cache hit, the write data in the write data register 15 is selected by the write bus selection circuit 16. Select it and run the cache scan.

Each cycle has been explained above, and although the request and actual cache access sequence are different in the above example, the addresses are different, so data consistency is maintained. Further, even if the store address (B) and the fetch address (C) indicate the same block, data consistency can be guaranteed by giving priority to the store pending request in the priority order determining circuit 5.

In the embodiment described in -F, the store pending request flag 13 is used both when write data is being sent to the write data bus 90 and when it is loaded into the write data buffer register 15. However,
You may have more than one of these. At the same time, a plurality of address registers 10 and write data buffer registers +5 may be provided.

In addition, although the above embodiment does not touch on the case of cache miss, cache miss handling is handled by cache.
Row 7 may also be performed depending on the result of the hit detection circuit.

In this way, when generating write data, a tag search is performed according to the cache store address, and if a cache hit is detected and a cache miss occurs, the hit state is restored by accessing the main memory and updating the cache memory. After that, the cache store valid address is held and a flag indicating its validity is set, and in the actual cache store cycle, the cache set is determined by checking the flag. Therefore, when writing data is generated, the data can be written to the cache memory without performing a tag search, and the store operation can be performed at high speed with a minimum of machine cycles. In addition, the overhead of cache access due to waiting during generation of S-included data is reduced, and performance can be improved.

〔Effect of the invention〕

As described above, according to the present invention, tag search, which is essential for cache store operation, is preceded and tag search is separated from cache data generation, thereby reducing the time required to actually write cache data. Since this method does not require tag searches, it is possible to perform cache store operations at high speed with a minimum of machine cycles, and also improves performance by reducing cache access overhead caused by waiting for write data generation. It has the effect of being measurable.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a cache store control method according to an embodiment of the present invention, FIG. 2 is an explanatory diagram showing detailed operation of the circuit in FIG. 1, and FIG. 3 is a diagram showing a conventional cache store control method. FIG. l...Cache memory 2...Address register 4...Hit detection circuit 5...Priority determination circuit 6...Write control Circuit 10...Store address register 11...
... Address selection circuit 12 ... Cache store validity determination circuit 1
4...Store address valid flag 15...
...Write data buffer register 16...
. . .Write bus selection circuit In the drawings, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] In a cache store control method for a computer with a cache memory, there is an address register that holds the cache access address, a store address register that holds the address at the time of cache store, and the validity of the store address. It is equipped with a determination circuit that determines whether the write data is correct, and a data register that holds write data to the cache memory, and performs a tag search of the cache memory according to the store address before generating the write data, and generates the write data. A cache store control method characterized in that the data is written to a cache memory at certain times.