JPH02259946A - Separation control system for cache memory - Google Patents

Abstract

PURPOSE:To enable the processing of data to be continued by transferring data in a move-in buffer to a main memory device when a cache memory falls in an unavailable state and the move-in buffer is valid and also, is set at an updating state. CONSTITUTION:When the cache memory 3 is separated due to a fault, etc., in the processing of a storing instruction for the main memory device, a request to read out block data is issued to the main memory device, and when preceding move-in data is stored in the move-in buffer 8 and it is discriminated that registered data is valid and also, it is set at the updating state, the move-in data is transferred to the main memory device. When the transfer of the data is completed and the move-in buffer 8 becomes the null state, storing data from an instruction processor is written on the move-in buffer 8. Thereby, it is possible to operate the instruction processor even when the cache memory is separated, and to continue the processing of the data.

Description

[Detailed Description of the Invention] [Summary] Regarding a cache memory isolation control method using a move-in buffer, processing is continued by operating an instruction processing unit even when the cache memory is in an unusable state. A storage control circuit having a cache memory and a move-in buffer for temporarily holding data transferred from a main storage device to the cache memory, wherein the cache memory is used. a first determining means for determining that the move-in buffer is in an impossible state; a second determining means for determining that the move-in buffer is valid; and a third determining means for determining that the move-in buffer is in an updated state. and, when the cache memory is in an unusable state and the move-in buffer is valid and in an updated state, the data in the move-in buffer is transferred to the main storage device. Configured.

[Industrial Application Field] The present invention relates to a cache memory isolation control method using a move-in buffer.

BACKGROUND ART Cache memory has been widely used as a means of improving the performance of computer systems, and a store-in method (also called a swap method) is widely known as one control method for cache memory.

In the store-in method, if the block to be stored is registered in the cache memory when the store occurs (
This state is called a cache hit state), the store data is written only to the cache memory, and if the target block is not registered in the cache memory (this state is called a cache miss state), the target block is written to the main memory. This method writes store data only to the cache memory after making a request to the device and registering it in the cache memory. According to this method, the control circuit is more complicated than, for example, a method called a store-through method, but since the operating rate of the main memory device is lower, it is especially important to share the main memory device with multiple instruction processing devices. When a so-called multiprocessor system is configured, there is an advantage that performance is improved compared to a single store-through system.

By the way, when there is no data in the cache memory in response to a memory request from the instruction processing unit, a so-called move-in is performed in which the data is read from the main memory and registered in the cache memory, but when there is a response from the main memory, At the same time, only the necessary data is responded to the instruction processing unit, and the response data from the main memory is not immediately registered in the cache memory, but is stored in a buffer storage called a move-in buffer and cached next time. By registering the move-in buffer data in the cache memory in the empty cycle when a miss occurs and waiting for a response from the main memory, the time occupied by the cache memory for registration is eliminated, and the performance of the instruction processing unit is improved. There are known methods that can improve this.

Here, if the cache memory becomes unusable, the instruction processing device becomes unable to operate.

Therefore, it is necessary to continue processing even if a failure occurs in the cache memory.

[Prior Art] In a cache memory using a store-in method, especially in processing a store instruction, when a block to be stored is not registered in the cache memory, a move-in is performed, and after storing it in a move-in buffer, a rough process is performed. Registration to the cache memory is started, and after registration is completed, store data is written to the cache memory.

[Problems to be Solved by the Invention] However, in such a conventional store-in type cache memory, for example, when processing a store instruction, a block to be stored must be registered in the cache memory. There has been a problem in that when the cache memory is in an unusable state, the instruction processing device cannot operate and cannot continue processing.

The present invention has been made in view of such conventional problems, and provides a cache memory disconnection method that allows an instruction processing unit to operate and continue processing even when the cache memory is in an unusable state. The purpose is to provide a control method.

[Means to solve the problem] FIG. 1 is a diagram explaining the principle of the present invention.

In FIG. 1, 3 is a cache memory, 8 is a move-in buffer for temporarily holding data transferred from the main storage device to the cache memory 3, and 16A is for determining that the cache memory 3 is in an unusable state. 16B is a second determining means for determining whether the move-in buffer 8 is valid; 16C is a third determining means for determining that the move-in buffer 8 is in an updated state.
It is a means of discrimination.

[Operation] When processing a store instruction to the main memory, if the cache memory becomes unusable due to a failure or the like and the cache memory is disconnected, a request is made to the main memory to read block data, and If the previous move-in data is stored in the move-in buffer and it is determined that the registered data is valid and in an updated state, this move-in data is transferred to the main storage device.

After the transfer to the main storage device is completed and the move-in buffer becomes empty, the store data from the instruction processing device is written to the move-in buffer. This completes the processing of the store instruction, and the instruction processing device starts processing the next instruction. Thereafter, the storage control circuit writes the move-in data from the main memory to the move-in buffer when there is a response from the main memory.

In this way, store instructions can be executed without using the cache memory, and furthermore, the instruction processing device can be operated even when the cache memory is disconnected.

As a result, data processing can continue.

[Example] Embodiments of the present invention will be described below based on the drawings.

FIGS. 2 and 3 are diagrams that do not show one embodiment of the present invention.

In FIG. 2, reference numeral 1 denotes an access address register into which the access address from the instruction processing device is input, and the access address register 1 is composed of, for example, 32 bits, and has an ID section, an index section, an intra-block address section, etc. ing. Access address register 1 is tag memory 2,
The address is output to the cache memory 3 and move-in buffer 7 address register 4. The tag memory 2 is indexed with an address index section. The tag memory 2 contains the address I of the block registered in the cache memory 3.
It has a bit called the D section and a bit indicating whether the block is valid or invalid, and the ID section of the tag memory 2 and the ID section of the access address register 1 are compared in a comparison circuit 5, and the comparison result is detected in a match detection circuit 6. be done. At the same time as searching the tag memory 2, the address of the access address register 1 and the address of the move-in buffer 7 address register 4 are compared in the comparison circuit 7, and the comparison result is sent to the match detection circuit 6.
Detected in As a result of the comparison by the tag memory 2 and the move-in buffer address register 4, if the block to be accessed is registered in the cache memory 3, it is in the cache hit state and also registered in the move-in buffer 7 address register 4. In this case, the move-in buffer 7 is in a hit state, and if it is not registered in either the cache memory 3 or the move-in buffer address register 4, a cache miss state occurs.

8 is a move-in buffer (M16) for temporarily holding data transferred from the main storage device to the cache memory 3, and the move-in buffer 8 has a block size of 32 bytes and a line size of 8 bytes, for example. There is. Therefore, if the line size that can be transferred at one time is 8 bytes, 4τ clock cycles are required to transfer block data. The move-in data in move-in buffer B is transferred to cache memory 3 via selection circuit 9.

Reference numeral 10 denotes a byte mark register in which a store byte mark from the instruction processing device is set, and the byte mark stored in the byte mark register 10 is either directly input to the move-in buffer 8 via the byte mark selection circuit 11, or Alternatively, after being inverted by the inverting circuit 12, the signal is input to the move-in buffer 8 via the byte mark selection circuit 11.

When a cache miss occurs in the cache memory 3 during the execution of a store instruction, the store data from the instruction processing device is transferred to the move-in buffer 8 from the selection circuit 1.
3 in and out according to the direct store byte mark. When there is a response from the main memory, move-in data is written into the move-in buffer 8 from the main memory via the selection circuit 13 according to the byte mark inverted by the inversion circuit 12.

14 is a selection circuit for selecting move-in data from the main storage device or data from the move-in buffer 8; 15;
is the data from the selection circuit 14 or the cache memory 3
This is a selection circuit that selects data from. Selection circuit 15
The data is sent to the instruction processing unit as read data. The selection circuit 17 selects data from the cache memory 3 or data from the move-in buffer 8 and sends it to the main storage device as move-out data.

16 is a control section, and this control section 16 is connected to the coincidence detection circuit 6.
Controls reading and writing of the cache memory 3 and move-in buffer 8 based on the output from the
It has a function as first to third determining means 16A to 16C.

The first determining means 16A determines whether the cache memory 3 is unusable by inputting a bit signal indicating that the cache memory 3 is unusable. Second determining means 16
B determines whether the move-in buffer 8 is valid by inputting a bit signal indicating whether the move-in buffer 8 is valid. The third determining means 16C determines that the move-in buffer B is in the updated state based on the input of the bit signal indicating that the move-in buffer 8 is in the updated state.

Next, the operation will be explained.

The access address of the cache memory access request from the instruction processing device is set in the access address register 1. After this, if the cache memory 3 is not disconnected, the tag memory 2 is searched and compared with the move-in buffer address register 4, and a cache hit or cache miss is detected. If it is, there will always be a cache miss condition.

In this way, when the first determining means 16A determines that the cache memory 3 is in an unusable state due to a failure of the cache memory 3 or the like, the cache memory 3 is disconnected. The operation of store command processing when the cache memory 3 is separated will be explained based on FIG. 3.

In FIG. 3, at time τO, the access address from the instruction processing device is set in the access address register 1 as described above, and the tag memory 2 is searched and the move-in buffer address register 4 is compared. Since it is disconnected, a cache miss state occurs, and a cache miss detection flag in the storage control circuit is set. While the flag is on, the instruction processing device delays instruction processing.

At the same time, it sends the address of the access address register 1 to the main memory and issues a read request for the main memory.

Next, at time τ1, the previous move-in data is registered in the move-in buffer 8, and the second and third determining means 16B and 16C determine that the registered data is valid and in an updated state. In this case, a move-out request is issued to the main storage device, and data in the move-in buffer 8 is transferred to the main storage device P from time τ1 to time τ4.

Next, at time τ5, when the instruction processing device is informed by a control signal that the move-in buffer 18 has become empty, the instruction processing device outputs store data and a store byte mark. The store data is selected by the selection circuit 13 of the move-in buffer 8 and written into and out of the move-in buffer 8 according to the store byte mark.

Second, the move-in buffer 8 is valid and in an updated state because the store data has been written to the move-in buffer 8. This is determined by the third determining means 16B and 16C, and the processing of the store instruction is completed, the cache miss flag is reset, and the instruction processing device starts executing the next instruction.

Next, when there is a response of move-in data from the main memory at time τn-3, the move-in data is selected by the selection circuit 13 of the move-in buffer 8 and stored in the store byte mark held in the byte mark register 10. The byte mark is inverted by the inverting circuit 12, and the data is read into the move-in buffer 8.

The remaining move-in data is written to move-in buffer B roughly from time τn-2 to time τn. This ends the move-in and also ends all processing.

Note that the operation from time .tau.n-3 to time .tau.n is carried out independently by the storage control circuit, and the instruction processing device can execute the instruction without any particular operation.

FIG. 4 is a time chart of the operation of another embodiment.

In this embodiment, a read request for the main memory is issued at time τO, and store data is written to the move-in buffer 8 at time τ1.

This is similar to the operation at time τ5 in the previous embodiment. Furthermore, at time τ1, is there a move-in buffer? 8 is guaranteed to always be empty.

Second, the move-in buffer 8 is valid and in an updated state because the store data has been written to the move-in buffer 8. This is determined by the third determining means 16B and 16C, and the processing of the store instruction is completed, the cache miss flag is reset, and the instruction processing device starts executing the next instruction.

Next, at time τn-7, when there is a response of move-in data from the host storage device, the move-in data is selected by the selection circuit 13 of the move-in buffer 8 and stored in the store byte held in the byte mark register 10. The byte mark inverted by the mark inversion circuit 12 is written into the move-in buffer 8.

The remaining move-in data is written into the move-in buffer 8 roughly from time τn-6 to time τn-4. This completes the move-in.

Next, the second. If the third determining means 16B and 16c determine that the data registered in the move-in buffer 8 is valid and in an updated state, a move-out request is issued to the main storage device and The data in the move-in buffer 8 is transferred to the main storage device between τ-3 and time τ. As a result, the move-in buffer 8 becomes empty.

In this way, when the cache memory 3 is in an unusable state, the store instruction can be executed without using the cache memory 3, and in general, the instruction processing device can be operated with the cache memory 3 disconnected. .

Note that in this embodiment, before writing move-in data to the move-in buffer 8, the move-in buffer 8 is
Although a case has been described in which store data is stored in the memory, the present invention is not limited to this, and store data may be stored after move-in data is written.

[Effects of the Invention] As explained above, according to the present invention, when the cache memory becomes unusable and the move-in buffer is valid and updated, the data in the move-in buffer is Since data is transferred to the storage device, store instructions can be executed without using cache memory, and the instruction processing device can be operated with the cache memory disconnected, allowing data processing to continue. can.

[Brief explanation of drawings]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a block diagram showing one embodiment of the invention, Fig. 3 is an operation time chart, and Fig. 4 is an operation time chart showing another embodiment. be. In the figure, 1...Access address register, 2...Tag memory, 3...Cache memory, 4...Move-in buffer address register, 5.7
...Comparison circuit, 6...-number output circuit, 8...Move-in buffer? , 9.13,14.15.17... selection circuit, 10...
- Byte mark register, 11... Byte mark selection circuit, 12... Inversion circuit, 16... Control unit, 16A... First discrimination means, 16B... Second discrimination means, 16C... Third discrimination means. Mokusan I! Tsuki no Fu, Chie 8 兇a Kami Diagram 1 Movement of Daimuna〒- Diagram 3

Claims (1)

[Claims] In a storage control circuit having a cache memory (3) and a move-in buffer (8) for temporarily holding data transferred from a main storage device to the cache memory (3), the cache memory (3) is not used. A first determining means (16A) for determining whether the move-in buffer (8) is enabled; a second determining means (16B) for determining whether the move-in buffer (8) is enabled;
) is in an updated state.
C), when the cache memory (3) is in an unusable state and the move-in buffer (8) is valid and in an updated state, the data in the move-in buffer (8) is A cache memory disconnection control method characterized in that data is transferred to the main storage device.