JPH05210534A - Instruction fetch trigger circuit - Google Patents

Abstract

PURPOSE:To detect a specific bus cycle in a specific routine by obtaining an instruction fetch trigger signal only in an instruction fetch cycle, ANDing it with a bus cycle coincidence signal, and obtaining a trigger signal. CONSTITUTION:An instruction fetch cycle detection part 13 detects whether a bus cycle generated with status information is the instruction fetch cycle or not. An address range detection part 14 detects whether or not the address of the generated bus cycle is within the range of a routine to be inspected. The contents of the address range detection part 14 are loaded in an instruction fetch trigger holding part 15 only in the instruction fetch cycle. The instruction fetch trigger signal generated by this instruction fetch trigger holding part 15 is used as a substitute for a sequence trigger together with the bus cycle coincidence signal and ANDed by an AND circuit 16 to obtain the trigger signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a trigger circuit for sampling the status of a data bus of a microprocessor, comparing it with preset data, and determining a match / mismatch status to obtain a trigger signal. In particular, the present invention relates to an in-circuit emulator trace function or an instruction fetch trigger circuit used in a state analyzer.

[0002]

2. Description of the Related Art An in-circuit emulator is a microprocessor development support having a function of arbitrarily executing / stopping a program, reading / writing of resources such as memory, and a trace function of execution by connecting to a target system instead of a microprocessor. Known as the device.

By the way, conventionally, in the trace function of such an in-circuit emulator or the state analyzer, the status of the data bus of the microprocessor is sampled every bus cycle, and the bus
The value of the data bus for each cycle is compared with a value preset from the outside, and the condition of the match / mismatch is judged and used for various triggers.

[0004]

However, in such a conventional method, for example, even if it is desired to trigger a memory write to the address 100 in a predetermined subroutine A, the address 100 in the subroutine A can be written. Memory of
I couldn't tell if it was a light or something else.

In order to avoid such a situation, recently, a function called a sequence trigger is used. This sequence trigger is a signal that sequentially tracks the sequence of bus cycle occurrences and indicates what the sequence is currently. By summing this signal and the comparison result for each bus cycle, the situation in which the bus cycle occurs is specified. For example, in the example where the memory write to the address 100 in the above-mentioned subroutine A is used as a trigger, the entrance and the exit of the subroutine A are set as the switching of the sequence, and after passing through this entrance, until the exit is reached. The purpose of this is to detect the memory write to the 100th address that has occurred in the above step.

However, this conventional sequence trigger may not be effective when the sequence detection becomes complicated. For example, it is difficult to detect that there are a plurality of entrances and exits of the subroutine A or that the routine is moved to another routine due to a hardware interrupt, and the setting becomes complicated.

Therefore, an object of the present invention is to provide an instruction fetch trigger circuit capable of detecting a specific bus cycle in a specific routine.

[0008]

In order to achieve the above object, an instruction fetch trigger circuit of the present invention samples the status of the data bus of a microprocessor, compares it with a preset comparison data, and makes a match. / In the instruction fetch trigger circuit for determining the mismatch condition and obtaining the trigger signal, the match is made by the bus cycle information generated by the microprocessor and the comparison bus cycle information set externally for detection. Detect the bus
By the bus cycle detection means for outputting a cycle coincidence signal and the status information of the microprocessor,
Instruction fetch cycle detecting means for detecting whether or not the generated bus cycle is an instruction fetch cycle and outputting an instruction fetch cycle signal, and address information generated by the microprocessor and a comparison address externally set The address range detecting means for comparing the information with the information to detect whether it is in the range to be inspected and outputting the address inside / outside signal, and the instruction fetch cycle signal and the address inside / outside signal, An instruction fetch that loads the result of the address inside / outside signal only for the instruction fetch cycle signal, retains the previous result when other cycles occur, and outputs the content as the instruction fetch trigger signal And AND between the trigger holding means and the bus cycle match signal and the instruction fetch trigger signal Those having an AND circuit for outputting a trigger signal out.

[0009]

According to the present invention, based on the instruction fetch cycle signal by the instruction fetch cycle detecting means and the address range inside / outside signal by the address range detecting means, the instruction fetch cycle is held by the instruction fetch trigger holding means. Only when the address range inside / outside signal is held, the instruction fetch trigger signal is obtained, and this instruction fetch trigger signal is used together with the bus cycle match signal instead of the sequence trigger, and the AND circuit calculates AND. To get the trigger signal,
The cycle is detected.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to an embodiment shown in the drawings. FIG. 2 is a diagram for explaining the configuration of the instruction fetch trigger circuit of the embodiment of the present invention.

In the figure, the instruction fetch and
The trigger circuit 11 includes a bus cycle detecting means 12, an instruction fetch / cycle detecting means 13, an address range detecting means 14, an instruction fetch / trigger holding means 15, and
It is composed of an AND circuit 16.

The bus cycle detecting means 12 is means for detecting a match between the bus cycle information and the comparison bus cycle information and outputting a bus cycle match signal. The instruction fetch cycle detecting means 13 is means for detecting an instruction fetch cycle from the status information and outputting an instruction fetch cycle signal. The address range detection means 14 is a means for detecting whether or not it is within the range of the inspection target based on the address information and the comparison address information, and outputting an address range inside / outside signal. The instruction fetch / trigger holding unit 15 loads the result of the address range inside / outside signal only in the case of the instruction fetch cycle signal by the instruction fetch cycle signal and the address range inside / outside signal, and fetches the contents of the instruction fetch cycle signal. It is a means for outputting as a trigger signal. The AND circuit 16 is a circuit that obtains the AND of the bus cycle match signal and the instruction fetch trigger signal and outputs the trigger signal.

FIG. 1 is an overall block diagram of an instruction fetch trigger circuit according to an embodiment of the present invention. This block diagram more specifically explains the instruction fetch / trigger circuit of FIG. 2, and the corresponding portions bear the same reference numerals.

In FIG. 1, the non-inspection target circuit is composed of a microprocessor (CPU) 21 and a peripheral circuit 22. The CPU 21 is, for example, a 32-bit CPU that has a wide data bus width and can handle a long data length, and has address information, data bus valid information, status information, dynamic bus sizing information, and data information, respectively. Are connected to the peripheral circuit 22 by lines that respectively supply the. The address information is information indicating the address content of the generated bus cycle. The data bus valid information indicates which byte boundary on the data bus of the generated bus cycle has valid information. For example, in a normal 32-bit CPU, a 32-bit data bus is used. Is divided into 4 bytes, and a data of any length such as 8, 16, 32, etc. can be made effective by combining a bus enable signal for selecting each byte and the lower 2 bits of the address signal. You can do it. Status information is
It shows the bus status information of the generated bus cycle, and is, for example, information related to the bus cycle definition such as read requesting to read or write requesting to write. The dynamic bus sizing information is information indicating what dynamic bus sizing has occurred in the generated bus cycle, and is information input from the peripheral circuit 22 to the CPU 21. The data information is information indicating the contents of the data bus.

The inspection side circuit is the instruction fetch / fetch circuit of this embodiment.
Trigger circuit 11, bus cycle desired trigger content setting unit 23, fetch trigger desired trigger content setting unit 24
It consists of and. The instruction fetch / trigger circuit 11 includes a bus cycle detection unit 12, an instruction fetch / cycle detection unit 13, an address range detection unit 14, an instruction fetch / trigger holding unit 15, and an AND circuit 16. The bus cycle desired trigger content setting section 23 is a section for setting desired trigger content, and all address / data / status information for comparison of the bus cycle to be detected is preset, and these information are compared. It is given to the bus cycle detection unit 12 as bus cycle information. The fetch trigger desired trigger content setting section 24
This is a part for setting desired trigger contents, and a range of addresses in which a predetermined routine to be compared is arranged is set in advance, and this information is given to the address range detector 14 as comparison address information.

The bus cycle detector 12 receives address information, data bus valid information, status information, which is given from the CPU 21 side as the generated bus cycle information.
A function of detecting a bus cycle match based on the dynamic bus sizing information, the data information, and the comparison bus cycle information provided from the bus cycle desired trigger content setting section 23, and outputting a bus cycle match signal. Is a part having.

The instruction fetch / cycle detection unit 13 uses C
It is a part having a function of detecting whether or not the generated bus cycle is an instruction fetch cycle based on the status information given from the PU 21 side and outputting an instruction fetch cycle signal as a result.

The address range detector 14 is provided with address information, data bus valid information, which is provided from the CPU 21 side.
Based on the dynamic bus sizing information and the comparison address information provided from the trigger desired trigger content setting unit 25, it is detected whether the address of the generated bus cycle is within the range of the routine to be inspected, and the result is detected. It is a part having a function of outputting as a signal within or outside the address range.

The instruction fetch / trigger holding unit 15 compares the instruction fetch cycle signal with the address range inside / outside signal, loads the result of the address range detecting unit 14 only in the case of the instruction fetch cycle, and fetches the instruction fetch. When a cycle other than the cycle occurs, the previous result is held and the content is output as an instruction fetch trigger signal.

The AND circuit 16 is a circuit that calculates the AND of the bus cycle match signal and the instruction fetch trigger signal to obtain the trigger signal.

Next, the operation of the instruction fetch / trigger circuit 11 having the above configuration will be described. First, the bus cycle detection unit 12 matches the currently occurring bus cycle based on the address information, the data bus valid information, the status information, the dynamic bus sizing information, the data information, and the comparison bus cycle information. Is detected. The instruction fetch cycle detection unit 13 detects whether the bus cycle generated by the status information is an instruction fetch cycle. The address range detection unit 14 determines whether the address of the generated bus cycle is within the range of the routine to be inspected, based on the address information, the data bus valid information, the dynamic bus sizing information, and the comparison address information. To be detected. The instruction fetch / trigger holding unit 15 loads the result of the address range detection unit 14 only during the instruction fetch cycle, and holds the previous result when a cycle other than the instruction fetch cycle occurs. The instruction fetch trigger signal generated from the instruction fetch trigger holding unit 15 indicates whether the bus cycle currently being generated is inside or outside the routine to be detected. Since this instruction fetch trigger signal indicates that the existence of the detection target routine is recognized as a range, the setting method does not change even if there are many entrances and exits of the routine, and hardware interrupts etc. Even if the routine is exited, detection is possible because the instruction fetch trigger signal indicates out of range in the first instruction fetch cycle of the interrupt routine. Therefore, the instruction fetch trigger signal
It is possible to detect a specific bus cycle in a specific routine by using the AND circuit 16 instead of the trigger and calculating AND with the AND circuit 16 and obtaining the trigger signal.

That is, in the conventional method, the flow of the program is to be understood as between the occurrence of an event for each bus cycle, such as the occurrence of one bus cycle to the occurrence of another bus cycle. In this embodiment, the problem is solved by detecting the flow of the program as a surface by detecting the range and holding the result.

In each of the above embodiments, a 32-bit CPU has been mainly described, but the present invention is not limited to this and can be applied to 8-bit, 16-bit and 64-bit CPUs.

[0024]

As described above, according to the present invention, the instruction fetch trigger is generated based on the instruction fetch cycle signal by the instruction fetch cycle detecting means and the address range inside / outside signal by the address range detecting means. The holding means holds the address range inside / outside signal only during the instruction fetch cycle to obtain the instruction fetch trigger signal,
This instruction fetch trigger signal is used in place of the sequence trigger together with the bus cycle match signal, and is calculated by the AND circuit, and the trigger signal is obtained, so that the specific bus cycle in the specific routine is detected. There is an effect that becomes possible.

[Brief description of drawings]

FIG. 1 is an overall block diagram of an instruction fetch trigger circuit according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration of an instruction fetch / trigger circuit according to an embodiment of the present invention.

[Explanation of symbols]

 11 instruction fetch / trigger circuit 12 bus cycle detecting means 13 instruction fetch / cycle detecting means 14 address range detecting means 15 instruction fetch / trigger holding means 16 AND circuit 21 CPU 22 peripheral circuit 23 bus cycle desired trigger content setting section 24 fetch・ Trigger desired trigger content setting section

Claims (1)

[Claims] 1. An instruction fetch trigger circuit for sampling the status of a data bus of a microprocessor, comparing it with preset comparison data, and determining a match / mismatch status to obtain a trigger signal. Bus cycle detecting means for detecting a match between the generated bus cycle information and the comparison bus cycle information externally set for detection, and outputting a bus cycle match signal; The instruction fetch cycle detecting means for detecting whether the generated bus cycle is the instruction fetch cycle or not and outputting the instruction fetch cycle signal, and the address information generated by the microprocessor and the external device. The range of the inspection target is compared by comparing with the comparison address information that is set. The address range detection means for detecting whether the address is within the range and outputting the address range inside / outside signal, and the instruction fetch cycle signal and the address range inside / outside signal, the address only in the case of the instruction fetch cycle signal Instruction fetch trigger holding means for loading the result of the in-range / outside signal, holding the previous result when another cycle occurs, and outputting the content as an instruction fetch trigger signal; An instruction fetch trigger circuit comprising: an AND circuit that calculates an AND of a cycle match signal and an instruction fetch trigger signal and outputs a trigger signal.