JPS58105359A - Measuring system of program processing time - Google Patents

Abstract

PURPOSE:To measure processing time of a program, by adding a small quantity of a software to a data processor containing an address coincidence detecting mechanism. CONSTITUTION:A CPU1 fetches an instruction or data within a memory 2. An address coincidence detecting mechanism 4 includes an address data setting circuit 5, a data comparator 6 and a data coincidence signal output circuit 7. The comparator 6 compares the address data set at the circuit 5 with an address data on an address bus and then informs a coincidence signal to the circuit 7 when the coincidence is obtained between both data. Thus the circuit 7 delivers a pulse signal, and this signal is displayed on a synchroscope 8.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention is directed to a data processing device having an address-dispersion output circuit, in which the processing time of four programs can be measured by software processing. 0 (2) Prior art and problems A known method of determining the processing time of a program is to find the number of steps in the program and calculate it from the number of steps. In some cases, a monitor or the like is involved, so complex calculations are required to determine the processing time from the number of program steps. In addition, the address scattering mechanism monitors all the address data on the address bus. For example, from time T1 when address data AI appears on the addressing bus, the address data A! It is also possible to consider a method of measuring the time until the time point T when T appears, but such a method has the disadvantage of requiring a plurality of address setters.

(3) Purpose of the Invention The present invention eliminates the above-mentioned disadvantages, and by simply adding a small amount of software to a data processing device having an address-distribution mechanism, the program processing time can be completely reduced. The objective is to provide a method for measuring program processing time that can be measured.

(4) Structure of the invention and therefore, the program processing time measuring method of the present invention includes a central processing unit, a memory, and an address-distribution mechanism, and the address coincidence detection mechanism detects addresses on an address bus. - When measuring the processing time of the program program part from address ■ to address ■ in a system configured to output a match signal when data and set address data match.

An instruction for branching to the original instruction tube address TESTI at address ■ and saving the address of the next instruction in a register, replacing it with a ninth instruction, branching to address CHECK and saving the address of the next instruction in the register,
Write an instruction string containing the original instruction at address ■ and an instruction for address trap branching indicated by the contents of the register to address TESTI, and the instruction tube address for branching to the address indicated by the non-operation instruction and the contents of the register. Write to CHECK.

Replace the original instruction at address ■ with an instruction to branch to address TEST2 and save the address of the next instruction in all registers, and a ninth instruction to branch to address CHECK and save the address of the next instruction in the registers, Instruction interest address T containing the original instruction at address ■ and an instruction to branch to the address indicated by the register
It is characterized by writing to EST2 and setting the address CHECK to the setting address of the address scattering mechanism.

(5) Examples of the invention The present invention will be explained below with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of the hardware configuration according to the present invention, FIG. 2 is a diagram showing a pulse waveform on a synchroscope, and FIG. 3 is a diagram showing an embodiment of the software configuration according to the present invention. .

In FIG. 1, it; i central processing unit; 2, memory;
3 is an address path, 4 is a tl address-scattering mechanism, 5 is
is an address/data setting circuit, 6 is a data comparison circuit, and 7 is an address/data setting circuit.
Reference numeral 8 indicates an address match signal output circuit, and 8 indicates a synchroscope.

The central processing unit l fetches instructions and data in the memory 2 and executes the instructions. The address/scattering output mechanism 4 has an address/data setting circuit 5, a data comparison circuit 6, and a data coincidence signal output circuit 7. Data comparison circuit 6
compares the address data set by the address/data setting circuit 5 with the address data on the address bus, and when the two match, notifies the data match signal output circuit 7 of the match. When the data match signal output circuit 7 is notified of the match, it outputs a pulse signal tube, and this pulse signal is displayed on the synchroscope 8. FIG. 2 shows the pulse waveform on the synchroscope 8.

FIG. 3 shows an embodiment of the 27-toe configuration according to the present invention. In FIG. 3, the points at which it is desired to measure the entire processing time are from ■ to [F]. First, it is converted to the instruction tube BAL TESTI of address 0. This instruction sets all address registers of the primary instruction and branches to TESTI. TESTI is the address where the instruction below the empty area eζ of the memory is set. 0 TESTI BAL CHECK This is an instruction for unconditionally branching to the next address specified by the contents of ! J.C.
HECK is an address where the following instructions are set in an empty area on the memory.

CHECK NOP RET Here, NOP is a command indicating no operation. Change the instruction at address (2) to BAL T'EST2. Here, TEST2 is the address where the following instruction is set in the empty area of the memory. 0 TEST2 BAL CHECK [F]' RET ω is the instruction to execute the instruction placed in the part 2.

When the program in Figure 3 starts executing and the instruction at address 0 is executed, it branches to TE)STI, then CHE
The program branches to CK, then the instruction ``■'' is executed, and then the routine returns.

When the main routine is executed and the instruction at address ■ is executed, the program branches to TEST2, branches to CHECK, executes the instruction at α, and returns to the main routine. By setting the address CHECK in the address/data setting circuit 5 shown in FIG. 1, it is possible to measure the time required to execute the program portion from point ω to point ■.

(6) Effects of the invention As is clear from the above description, the present invention has the following features.

It has advantages such as requiring a simple hardware configuration and requiring only a small amount of additional software configuration. In the above explanation, it was between the two points from ■ to ■, but if the ■ part TEST3 is added in the same way, the side leg between the three points @-■-■ becomes possible. Furthermore, according to the present invention, more detailed measurements can be performed by simply adding a check address branch condition at a checkpoint.

For example, if the aforementioned checkpoint 0 is in a common subroutine, the 0 point will be passed many times.

In that case, by adding a program to the TESTI section that branches to the check address only when the task uses this subroutine, program ■ becomes 0.
It will branch to the check address only when it passes through the section.

[Brief explanation of drawings]

#! Fig. 1 shows an embodiment of the hardware configuration according to the present invention, Fig. 2 shows a pulse waveform on a synchless jeep, and Fig. 3 shows an embodiment of the software configuration according to the present invention. It is a diagram. DESCRIPTION OF SYMBOLS 1...Central processing unit, 2...Memory, 3...Address bus, 4...Address-distribution mechanism, 5...
Address/data setting circuit, 6... data comparison circuit,
7...Address match signal output circuit, 8...Synchroscope. Tokken Applicant Fujitsu Limited Representative Patent Attorney Yotsubu Kyotani

Claims (1)

[Claims] It comprises a central processing unit, a memory, and an address-scattering output mechanism, and the address match detection mechanism outputs a match signal when the address-data on the address path matches the set address data. In the configured system, when measuring the processing time of a program portion from address ω to address 0, an instruction is used to branch the original instruction at address ω to address TESTI and to save the address of the next instruction in a register. Replaced with , an instruction to branch to address CHECK and save the address of the next instruction in a register, the original instruction at address ■, and an instruction string containing an instruction tube to branch to the address indicated by the contents of the register as address. Writes to TESTI, writes to the instruction t address CHECK to branch to the address indicated by the non-operation instruction and the contents of the register, branches to the original instruction tube address TEST2 of address ■, and writes the address of the next instruction to the register. An instruction string that replaces the instruction to save, branches to address CHECK, and saves in the address register of the next instruction, the original instruction at address ■, and an instruction tube to branch to the address indicated by the register. Write to the tube address TEST2, and set the setting address of the above-mentioned address-intermittent detection mechanism to address CHECK.
Featured program processing time measurement method