JPH04178840A - Performance measuring system - Google Patents

Abstract

PURPOSE:To attain real time measurement by an external monitor by reflecting the execution of a measurement start address of a program to be measured and the execution of its measurement end address to a signal change on an I/O port. CONSTITUTION:This performance measuring system is provided with a start address storing part 10, an end address storing part 11, an address comparing means 30, an I/O port setting part 50, an I/O port resetting part 51, an I/O port 60, and an I/O port address storing part 20. When a CPU 40 executes the instruction of the measurement start address, the I/O port 60 is set up, and at the time of executing the measurement end address instruction, the I/O port 60 is reset. Consequently, a time elapsed between the set and reset of the port 60 can be monitored by the external monitor connected to the port 60 and performance between the start and end addresses of the program to be driven by a CPU 40 can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a performance measurement method that supports the measurement of execution time performance of software using a microprocessor. A performance measurement method that connects a microprocessor to accurately measure software performance within a microprocessor device.

[Conventional technology]

Conventionally, this type of performance measurement method uses a timer (real timer or interval timer) built into the microprocessor device to read the difference between the measurement end point and the start point, or a dedicated device is installed on the bus of the microprocessor device. The most common method was to connect a device (logic analyzer, in-circuit emulator, etc.) to measure time.

[Problem to be solved by the invention]

The conventional performance measurement method described above has a drawback in that the former timer difference reading method can only read time differences that depend on the accuracy of the timer. Furthermore, since this type of timer value is read by software, it is difficult to accurately obtain the execution time of the software under test. On the other hand, the latter method using dedicated hardware has the disadvantage that the device is large-scale and has poor operability.

[Means to solve the problem]

The performance measurement method of the present invention includes a start address storage section that stores the start address of performance measurement, an end address storage section that stores the end address of performance measurement, and a program counter signal (hereinafter referred to as PC) output by the CPU. An address comparison means that compares the contents of its own start address storage section and end address storage section and outputs an address match signal when they match, and an I/O device that allows changes in the output signal to be easily observed from the outside.
O boat and an I/O boat that stores the address of the I/O boat.
an /O port address storage unit; an /O port setting unit that outputs a signal to the I/O boat using the start address outputted by the address comparing means and an address matching signal with the PC as a trigger; and (2)/O port reset section which outputs a reset signal to the (1)/O port using an address coincidence signal between the end address and the PC simultaneously outputted by the address comparing means as a trigger.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. Start address storage section /O and end address storage section 11
are registers in which the measurement start/end addresses of each performance measurement program are set in advance, and the address comparison means 30 compares the PC signal output from the CPU 40 with the contents of the start address storage section /O and the end address storage section 11. A'D
The means for outputting a reset signal to the I/O port 60 pointed to by the I/O port address storage section 20 using the E L signal as a trigger, the 1/○ port reset section 51 simultaneously
This means outputs an I/O boat 60 heliset signal using the 2 signal as a trigger.

Next, the operation of this embodiment will be explained. A program running using the CPU 40 roughly checks the measurement start address and end address, and first stores them in the start address storage section /O and the end address storage section 11.

When the block to be measured is run on the CPU 40 under this preparation, the PC information changes according to the execution order of the block to be measured. Here is the CPU 4. When O outputs a PC that matches the address stored in the start address storage section /O, the address comparing means 30 outputs an ADEI signal. At this point, a set signal (
S) or ■/O will be output from the boat set section 50. ■/'0 port address 20 is I, where signal changes can be easily observed from outside the device using this microprocessor.
By specifying the /O boat, this set signal (S) can be observed by an external monitor device. An example of such a J/O port is commonly implemented in a general-purpose computer using an ordinary microprocessor. For example, R
The 3232C interface port can be upgraded.

Next, when the PC outputs the address that matches the address stored in the end address storage section 11 on the CPU 40, the ADH2 signal is generated by the address comparison means 30, and this signal causes the I/O boat reset 1 to 51 or the I/O boat 60/\
Outputs a reset signal (R).

As can be seen from the above explanation, focusing on the output value of the 1/O port 60 indicated by the 1/○ port address storage section 20,
When the CPU 40 executes the instruction at the measurement start address ■
The /O port 60 is set, and when the CPU 40 executes the instruction for the measurement end address, the I/O port 60 is reset.

Therefore, by measuring the elapsed time between set and reset using an external monitor connected to the I/O boat 60, the CPU 4
It is possible to obtain the performance between the start and end addresses of a program running on 0.

The above description describes the most basic application example of the present invention, but it is also possible to provide multiple pairs of start/end address storage units to simultaneously measure multiple points I on the CPU 40. For example, if a certain condition is met by attaching conditions to the measurement of a program running on the CPU 40, for example, an application example such as a measurement method that separates the program into an O8 part and an AP part and makes it possible to measure only the AP part. Applicable.

Furthermore, although the address match signal in this embodiment has been explained using the instruction address match signal as an example, a system in which it is replaced with an operand address match signal is also an example of application of the present invention.

〔Effect of the invention〕

As explained above, the present invention executes the execution of the measurement start address and the measurement end address of the program under test.
This has the advantage that it can be reflected in the signal change of the O port and measured in real time by an external monitor.

Adopting this method has the advantage that all of the disadvantages of the conventional technology, such as low precision in measurement time and the need for dedicated hardware for accurate time measurement, can be overcome.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. /O・11...Measurement start 2/end address storage section, 2
0...■7'0 boat address section, 30...address comparison means, 40...cpu, 50...I, /O port set section, 51...■/O port reset section, 6°・
...I/O boat.

Claims (1)

[Claims] A start address storage section that stores the start address of performance measurement, an end address storage section that stores the end address of performance measurement, and a program counter signal (
(hereinafter referred to as a PC), an address comparing means that compares the contents of the start address storage section and the end address storage section and outputs an address match signal when they match, and an I/O device that allows changes in the output signal to be easily observed from the outside. an I/O port address storage unit that stores the address of the I/O port, the start address output by the address comparison means, and an address match signal between the PC and the I/O port. an I/O port setting unit that outputs a set signal to the I/O port; and an I/O port setting unit that outputs a reset signal to the I/O port using an address coincidence signal between the end address and the PC that is simultaneously output from the address comparing means as a trigger. O
A performance measurement method characterized by comprising a port reset section.