JP3691340B2 - Memory access control circuit - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a memory access control circuit, and more particularly to a memory access control circuit that accesses a memory in the same recording medium through a controller provided in a removable recording medium, for example.
[0002]
[Prior art]
As a recording medium that can be detachably attached to an electronic apparatus, there is a recording medium that accesses a semiconductor memory through a controller provided in the medium, such as a compact flash. Here, the access speed of the controller tends to increase as the memory capacity increases. In other words, when the increase in capacity of the semiconductor memory is realized by the advancement of technology, the access speed of the controller is also increased by the advancement of technology. When accessing such a recording medium, the prior art has set the active period of the access control signal to be given to the controller longer so that the access processing can be performed reliably even when a recording medium with a small capacity is loaded. .
[0003]
[Problems to be solved by the invention]
However, there is a problem that the performance of the controller cannot be exhibited sufficiently by setting the active period of the access control signal longer.
[0004]
SUMMARY OF THE INVENTION Therefore, a main object of the present invention is to provide a memory access control circuit capable of sufficiently exerting the performance of a controller provided in a recording medium.
[0005]
[Means for Solving the Problems]
  This inventionMemory access control circuit according toIsData including capacity value dataMemory to storeWhencontrollerWhenRecording medium comprisingIn the memory access control circuit that reads a desired data from the memory by giving a read control signal to the controller when the is mounted, the active period of the read control signal is set to a predetermined period in order to read the capacitance value data stored in the memory. 1 setting means, detection means for detecting the capacity of the memory based on the capacity value data read in connection with the setting operation of the first setting means, and reading a predetermined period when the capacity detected by the detection means is less than or equal to a threshold value First enabling means for enabling as an active period of the control signal, second setting means for setting the active period of the read control signal to a plurality of different periods when the capacitance detected by the detecting means exceeds a threshold value, second setting From the memory in relation to the setting operation of the meansRead outdataIs rightnoDetermining means for determining whether or notOf discrimination meansDiscrimination resultData can be legitimately read from memory based onActivate the shortest active period2With validation meansEach of the plurality of periods set by the second setting means is shorter than the predetermined period.
[0006]
[Action]
  The recording medium includes a memory for storing data including capacity value data and a controller. The operation of giving a read control signal to the controller and reading out desired data from the memory is executed when such a recording medium is loaded. The first setting means sets the active period of the read control signal to a predetermined period in order to read the capacitance value data stored in the memory. The capacity of the memory is detected by the detecting means based on the capacity value data read in connection with the setting operation of the first setting means. If the capacitance detected by the detection means is less than or equal to the threshold value, the first validation means validates the predetermined period as the active period of the read control signal. If the capacitance detected by the detection means exceeds the threshold value, the active period of the read control signal is set to a plurality of different periods by the second setting means. The discriminating unit discriminates whether or not the data read from the memory in relation to the setting operation of the second setting unit is valid. The second validation unit validates the shortest active period during which data can be legitimately read from the memory based on the discrimination result of the discrimination unit. Here, each of the plurality of periods set by the second setting means is shorter than the predetermined period.
[0007]
  In this way, data is read by a plurality of read control signals having different active periods.De-OfLegitimacy is determined,Data can be read legitimatelySince the shortest active period is activated, the performance of the controller is maximized.
[0008]
  In one example of this invention, the memoryIsRecording mediumIn betweenCommon common dayTStore andNoted in relation to the setting operation of the second setting meansRead control signalIssueCommon dayOfStorage locationofIncluding address information and the discriminating means reads the common data read from the memory.TWhether to show a predetermined valuenoIs determined.
[0011]
【The invention's effect】
  According to this invention,RecordThe performance of the controller included in the recording medium can be maximized.
[0012]
The above object, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.
[0013]
【Example】
Referring to FIG. 1, a data processing apparatus 10 of this embodiment includes a synchronous bus type CPU 12. The CPU 12 is connected to the camera ASIC 16 and the bidirectional buffer 20 via the data bus 14. The memory card 22 is connected to the bidirectional buffer 20 when inserted in the slot 24. The memory card 22 is provided with a controller 22 a and a memory 22 b, and the controller 22 a is connected to the bidirectional buffer 20. Therefore, access to the memory 22b is performed through the controller 22a. The memory card 22 is a recording medium such as a compact flash compatible with the PCMCIA format, and is detachably held in the slot 24.
[0014]
When reading data from the memory card 22, the CPU 12 outputs an address strobe signal (AS signal), a chip select signal (CS signal), an R / W signal for identifying access contents, and an address signal. Among them, the AS signal, CS signal, and R / W signal are supplied to the memory control circuit 18 provided in the camera ASIC 16, and the address signal is supplied to the memory card 22. The memory control circuit 18 generates a control signal (Wc0 signal, Wc1 signal), a CS signal, and an output enable signal (We signal) for the bidirectional buffer 20 in response to the input signal. As a result, a data signal is read from a desired address in the memory 22b, and the read data signal is output to the CPU 12 via the bidirectional buffer 20 and the bus 14. The camera ASIC 16 itself outputs a READY signal to the CPU 12 at a timing when the data signal is given to the CPU 12.
[0015]
Specifically, the CPU 12 processes the flowchart shown in FIG. First, it is determined in step S1 whether or not the memory card 22 is inserted in the slot 24. If not, a warning is displayed on a display (not shown) in step S3. On the other hand, if the memory card 22 is attached, the access time is set to the maximum value in step S5. Specifically, the CS signal, R / W signal, and address signal that are output by itself are set to the maximum active period, and a control signal is given to the camera ASIC 16 to activate the Wc0 signal, Wc1 signal, CS signal, and We signal. Set the period to the maximum value.
[0016]
In step S 7, the AS signal, the CS signal, and the R / W signal indicating “read” are supplied to the camera ASIC 16, and the address signal indicating the storage address of the ID data signal is supplied to the memory card 22. The controller 22a provided in the memory card 22 is supplied with a CS signal, a We signal, and an address signal whose active period is set to the maximum value, whereby an ID data signal is read from the ID storage address of the memory 22b. In step S9, the capacity value of the memory 22b is detected from the read ID data signal. That is, the ID data signal has common data common to all memory cards such as a model number and capacity value data indicating a capacity value. In step S9, the capacity value data is detected from the ID data signal.
[0017]
In step S11, it is determined whether the capacity value of the memory 22b is larger than a predetermined value (for example, 8 Mbytes) based on the detected capacity value data. If capacity value ≦ predetermined value, the process proceeds to the desired data signal access process in step S23. In other words, the maximum active period is determined as the optimum active period (maximum access time) by determining NO in step S11. As a result, in step S23, the CS signal, We signal, and address signal that maximize the active period are given to the memory card 22, and the access process is performed over the maximum access time.
[0018]
On the other hand, if it is determined in step S11 that the capacity value> predetermined value, the access time is reduced by one step in step S13. That is, the active period of the CS signal, R / W signal and address signal output by itself, and the active period of the Wc0 signal, Wc1 signal, CS signal and We signal output from the memory control circuit 18 are shorter by one step than the present time. Set to. In step S15, the memory card 22 is accessed in the same manner as in step S7 using various signals whose active period is reset, and the ID data signal is read from the memory 22b.
[0019]
In step S17, common data is detected from the read ID data signal, and in the subsequent step S19, the detected common data value is compared with a predetermined value to determine whether the ID data signal is valid. Here, if the common data value indicates a predetermined value, the ID data signal is regarded as being properly read (the ID data signal is regarded as valid), and the process returns to step S13. As a result of returning to step S13, the access time is further shortened by one step, and the ID data signal is read again with the shortened access time.
[0020]
As a result of shortening the access time, if the ID data signal is not properly read and the common data value shows a value different from the predetermined value, it is determined as NO (the read ID data signal is invalid) in step S19. In this case, the access time is extended by one step in step S21. That is, the ID data signal appropriately reads the active period of the CS signal, R / W signal and address signal output by itself, and the active period of the Wc0 signal, Wc1 signal, CS signal and We signal output from the memory control circuit 18. Set to the shortest possible period. As a result, the shortest active period during which the ID data signal can be appropriately read is determined as the optimum active period. When the optimum active period is determined, an access process for a desired data signal is executed in step S23.
[0021]
The memory control circuit 18 is configured in detail as shown in FIG. Further, when reading the ID data signal from the memory card 22 over the maximum access time, the CPU 12 and the memory control circuit 18 operate at the timing shown in FIG.
[0022]
The AS signal, CS signal, address signal, and R / W signal indicating “read” are output from the CPU 12 at the timings shown in FIGS. Both the AS signal and the CS signal are active-low signals. The access start circuit 24 receives the AS signal, the CS signal, and the R / W signal, and responds to the rise of the AS signal in response to the CS signal shown in FIG. 4 (F) and the access control window signal (FIG. 4G). Wa signal) is output. The CS signal and Wa signal are also active low signals, and are synchronized with the clock shown in FIG. The CS signal is given to the controller 22a, and the Wa signal is given to the access control counter 28, whereby both are activated. Note that the read destination address (ID storage address) of the memory 22b is specified by an address signal directly given from the CPU 12.
[0023]
The count value (Wb signal) of the counter 28 is incremented as shown in FIG. 4 (H) in response to the clock. Such a count value is given to the OE control circuit 30, the bidirectional buffer control circuit 32, the output buffer control circuit 34, the data latch control circuit 36, and the READY control circuit 38. The OE control circuit 30 generates an output enable signal (We signal) when the count value takes “1” to “5”, and this We signal is output at a timing shown in FIG. Is done. The bidirectional buffer control circuit 32 generates control signals (Wc0 signal, Wc1 signal) when the count value takes “0” to “5”, and these signals also pass through the latch circuit 42 as shown in FIG. ) Is output at the timing shown in FIG. Further, the output buffer control circuit 34 generates a control signal (Wd signal) when the count value takes “6” to “7”, and this Wd signal is also output at the timing shown in FIG. Furthermore, the data latch control circuit 36 generates a control signal (Wf signal) shown in FIG. 4M when the count value takes “6”. The READY control circuit 38 generates a READY signal when the count value takes “7”, and this READY signal is output via the latch circuit 46 at the timing shown in FIG.
[0024]
That is, the active low signals Wc0, Wc1, Wd, We, and READY are delayed by one clock by the latch circuits 40-46. On the other hand, the active high Wf signal is output without delay.
[0025]
The We signal output from the latch circuit 40 is given to the controller 22a. As described above, since the We signal is an active low output enable signal, the controller 22a reads the ID data signal from the memory 22b during a period when this signal is low level. The ID data signal is held for a short period after the rising of the We signal, and the ID data signal read timing is expressed as shown in FIG. On the other hand, the Wc0 signal and the Wc1 signal output from the latch circuit 42 are applied to the bidirectional buffer 20. The bidirectional buffer 20 is powered on by the Wc0 signal, and the buffer 20a is disabled and the buffer 20b is activated by the Wc1 signal. Accordingly, data can be transferred from the memory card 22 side to the data bus 14 side only during the period A shown in FIG. As a result, the read ID data signal (data Da) passes through the bidirectional buffer 20 and the data bus 14 at the timing shown in FIG. 4 (O) and is input to the memory control circuit 18.
[0026]
The data Da is given to the latch circuit 50 through the buffer 48, and is latched at the rising edge of the clock during the rising period of the Wf signal output from the data latch control circuit 36. That is, the data Da is latched when the count value reaches “7”. Assuming that the latched ID data signal is Db, the data Db is output from the latch circuit 50 at the timing shown in FIG. 4 (N) and input to the buffer 54 via the selection circuit 52. The buffer 54 is activated in the period B shown in FIG. 4 by the Wd signal output from the latch circuit 44, and outputs the data Db to the data bus 14 only during this period B. As a result, the ID data signal transferred on the data bus 14 is switched from Da to Db at the timing shown in FIG.
[0027]
The READY signal is output from the latch circuit 46 when the count value reaches “8”. This READY signal is given to the access start circuit 24 and the counter 28 in addition to the CPU 12. The access start circuit 24 is disabled at the rising edge of the READY signal, thereby stopping the output of the CS signal and the Wa signal. The counter 28 is reset at the rising edge of the READY signal. As a result, the controller 22a is disabled two clocks after the data Da is latched. On the other hand, the CPU 12 takes in the data Db at the rising edge of the clock during the input period of the READY signal, and stops outputting the AS signal, CS signal, R / W signal, and address signal at the rising edge of the READY signal.
[0028]
When the access time is shortened by one step, the CPU 12 and the memory control circuit 18 operate at the timing shown in FIG.
[0029]
The AS signal, CS signal, address signal, and R / W signal are output from the CPU 12 at the timings shown in FIGS. Here, the active periods of the CS signal, the address signal, and the R / W signal are shorter by one clock period than those in FIGS. 4B to 4E. The access start circuit 24 outputs the CS signal shown in FIG. 5F and the Wa signal shown in FIG. 5G in response to the rising edge of the AS signal. The CS signal and the Wa signal are also shorter by one clock period compared to FIGS. 4 (F) and 4 (G).
[0030]
The count value (Wb signal) of the counter 28 is incremented at the timing shown in FIG. The OE control circuit 30 generates a We signal when the count value takes “1” to “4”, and this We signal is output through the latch circuit 40 at the timing shown in FIG. The bidirectional buffer control circuit 32 generates a Wc0 signal and a Wc1 signal when the count value takes “0” to “4”, and these signals also pass through the latch circuit 42 and have the timing shown in FIG. Is output. Further, the output buffer control circuit 34 generates a Wd signal when the count value takes “5” to “6”, and this Wd signal is also output at the timing shown in FIG. Furthermore, the data latch control circuit 36 generates the Wf signal shown in FIG. 5M when the count value takes “5”. The READY control circuit 38 generates a READY signal when the count value takes “6”, and this READY signal is output via the latch circuit 46 at the timing shown in FIG.
[0031]
That is, the active period of the Wc0 signal, the Wc1 signal, and the We signal is shortened by one clock compared to FIGS. 4I and 4K. For the Wd signal, the Wf signal, and the READY signal, the timing at which the signal becomes active is advanced by one clock period.
[0032]
The controller 22a reads the ID data signal from the memory 22b at the timing shown in FIG. The buffer 20b is activated in the period A shown in FIG. 5 by the Wc1 signal. For this reason, the ID data signal (data Da) read from the memory 22b passes through the bidirectional buffer 20 and the data bus 14 at the timing shown in FIG. The data Da is given to the latch circuit 50 through the buffer 48, and is latched at the rising edge of the clock in the rising period of the Wf signal. That is, the data Da is latched when the count value becomes “6”. The latched ID data signal (data Db) is output from the latch circuit 50 at the timing shown in FIG. 5 (N) and input to the buffer 54 via the selection circuit 52. The buffer 54 is activated in the period B shown in FIG. 5 by the Wd signal, and outputs the data Db to the data bus 14 only during the period B.
[0033]
A READY signal is output from the latch circuit 46 when the count value reaches “7”. The output of the CS signal and the Wa signal from the access start circuit 24 is stopped in response to the rise of the READY signal, and the counter 28 is also reset at the rise of the READY signal. On the other hand, the CPU 12 takes in the data Db at the rising edge of the clock during the input period of the READY signal, and stops outputting the AS signal, CS signal, R / W signal, and address signal at the rising edge of the READY signal.
[0034]
When the access time is further shortened by one step, the CPU 12 and the memory control circuit 18 operate at the timing shown in FIG.
[0035]
The CPU 12 outputs an AS signal, a CS signal, an address signal, and an R / W signal at the timings shown in FIGS. 6B to 6E. As can be seen from comparison with FIGS. 5B to 5E, the active periods of the CS signal, the address signal, and the R / W signal are shortened by one clock period. The access start circuit 24 outputs the CS signal shown in FIG. 5 (6) and the Wa signal shown in FIG. 6 (G) in response to the rising edge of the AS signal. The CS signal and the Wa signal are also shorter by one clock period than FIGS. 5 (F) and 5 (G).
[0036]
The count value (Wb signal) of the counter 28 is incremented at the timing shown in FIG. The OE control circuit 30 generates a We signal when the count value takes “1” to “3”, and the generated We signal is output from the latch circuit 40 at the timing shown in FIG. The bidirectional buffer control circuit 32 generates the Wc0 signal and the Wc1 signal when the count value takes “0” to “3”, and the Wc0 signal and the Wc1 signal are also latched at the timing shown in FIG. 42. Further, the output buffer control circuit 34 generates a Wd signal when the count value takes “4” to “5”, and this Wd signal is also output from the latch circuit 44 at the timing shown in FIG. Furthermore, the data latch control circuit 36 generates the Wf signal shown in FIG. 6 (M) when the count value takes “4”. The READY control circuit 38 generates a READY signal when the count value takes “5”, and this READY signal is output from the latch circuit 46 at the timing shown in FIG.
[0037]
As described above, the active periods of the Wc0 signal, the Wc1 signal, and the We signal are shortened by one clock compared to FIGS. 5 (I) and 5 (K). For the Wd signal, the Wf signal, and the READY signal, the timing at which the signal becomes active is advanced by one clock period.
[0038]
Upon receiving the We signal shown in FIG. 6K, the controller 22a reads the ID data signal (data D) from the memory 22b at the timing shown in FIG. 6L. Since the buffer 20b is activated in the period A shown in FIG. 6 by the Wc1 signal, the read data Da passes through the bidirectional buffer 20 and the data bus 14 at the timing shown in FIG. Input to the circuit 18. The data Da is given to the latch circuit 50 through the buffer 48, and is latched at the rising edge of the clock in the rising period of the Wf signal. That is, the data Da is latched when the count value reaches “5”. The latched ID data signal (data Db) is output from the latch circuit 50 at the timing shown in FIG. 6 (N) and input to the buffer 54 via the selection circuit 52. The buffer 54 is activated in the period B shown in FIG. 6 by the Wd signal, and outputs the data Db to the data bus 14 only during this period B.
[0039]
The READY signal is output from the latch circuit 46 when the count value becomes “6”. The output of the CS signal and the Wa signal from the access start circuit 24 is stopped in response to the rise of the READY signal, and the counter 28 is also reset at the rise of the READY signal. On the other hand, the CPU 12 takes in the data Db at the rising edge of the clock during the input period of the READY signal, and stops outputting the AS signal, CS signal, R / W signal, and address signal at the rising edge of the READY signal.
[0040]
According to this embodiment, when the data signal is read from the memory card held in the slot, the address signal, CS signal and We signal in the maximum active period are first supplied to the controller, and the ID data signal is received from the ID storage address of the memory. Read out. This ID data signal includes memory capacity value (total capacity value) data. Based on this capacity value data, it is determined whether the memory capacity is larger than a predetermined value. If the capacitance value is equal to or less than the predetermined value, the maximum active period is determined as the optimum active period. That is, the maximum active period is activated.
[0041]
On the other hand, if the capacitance value is equal to or greater than the predetermined value, the ID data signal is read from the memory by the address signal, CS signal, and We signal having different active periods, and each read ID data signal is validated. Is determined. Specifically, the value of the common data included in the ID data signal is compared with a predetermined value, and if the common data value indicates the predetermined value, it is determined that the ID data signal is valid. If ID is not indicated, it is determined that the ID data signal is invalid. Then, the shortest active period is determined as the optimum active period among the active periods when the ID data signal determined to be valid is read. That is, the shortest active period during which the ID data signal is appropriately read out is validated.
[0042]
As described above, the maximum active period is enabled if the memory capacity is equal to or smaller than the predetermined value, and the shortest active period in which the data signal can be appropriately read is enabled if the memory capacity is larger than the predetermined value. ing. For this reason, when a memory card with a capacity less than or equal to a predetermined value is inserted, the time until the desired data can be accessed can be shortened. When a memory card with a capacity exceeding the predetermined value is installed, the controller Can be fully utilized.
[0043]
In this embodiment, when the shortest active period during which the ID data signal can be appropriately read out is obtained, the active period is shortened by one step. However, the active period is extended by one step and the above shortest active period is obtained. The active period may be obtained. In this embodiment, a compact flash is used as a recording medium. However, a micro drive or a memory stick may be used instead of the compact flash. Further, in this embodiment, the output timing of the control signals Wc0, Wc1, Wd, We, Wf and the READY signal is controlled by the counter, but a state machine other than the counter may be used for the timing control.
[0044]
Although only the read operation has been described in this embodiment, the present invention is also effective for the write operation.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a flowchart showing a part of the operation of FIG. 1 embodiment;
FIG. 3 is a block diagram showing a memory control circuit.
FIG. 4 is a timing diagram showing a part of the operation of the embodiment in FIG. 1;
FIG. 5 is a timing diagram showing another part of the operation of the embodiment in FIG. 1;
FIG. 6 is a timing chart showing another part of the operation of the embodiment in FIG. 1;
[Explanation of symbols]
10: Data processing device
12 ... CPU
14 Data bus
18. Memory control circuit
20 ... Bidirectional buffer
22 ... Memory card

Claims (3)

In the memory access control circuit for reading out desired data from said memory by applying a read control signal to the controller when the recording medium is mounted and a memory and a controller for storing data including the capacitance value data,
First setting means for setting an active period of the read control signal to a predetermined period in order to read the capacitance value data stored in the memory;
Detecting means for detecting the capacity of the memory based on capacity value data read in association with the setting operation of the first setting means;
First enabling means for enabling the predetermined period as an active period of the read control signal when the capacitance detected by the detecting means is less than or equal to a threshold;
Second setting means for setting an active period of the read control signal to a plurality of different periods when the capacitance detected by the detection means exceeds the threshold;
Determining means for determining whether the data read from the memory in relation to the setting operation of the second setting means is valid; and validating the data from the memory based on the determination result of the determining means A second enabling means for activating the shortest active period that can be read ,
Each of the plurality of period set by the second setting means you being shorter than the predetermined period, the memory access control circuit. Wherein the memory stores a common data which is common among records medium,
Read control signal of interest in connection with the setting operation of the second setting means includes a storage destination address information of the common data,
It said determining means said common data read from the memory it is determined whether or not indicating the predetermined value, the memory access control circuit according to claim 1. A data processing apparatus comprising the memory access control circuit according to claim 1.

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