JP3523059B2 - Horizontal synchronization signal frequency detection method and horizontal synchronization signal frequency detection circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a horizontal synchronizing signal frequency detecting method and a horizontal synchronizing signal frequency detecting circuit suitable for a control microcomputer used in, for example, a multi-scan CRT display monitor or a liquid crystal display monitor.

[0002]

2. Description of the Related Art In various types of computer devices connected to a multi-scan display, the frequencies of horizontal synchronizing signals and vertical synchronizing signals of video signals are often different. Therefore, in the multi-scan display, in order to display the data from the computer device connected thereto, the frequency of each of the horizontal synchronizing signal and the vertical synchronizing signal is detected, and the frequency of each of the detected horizontal synchronizing signal and the vertical synchronizing signal is detected. Following this, it is necessary to control the horizontal deflection circuit and the vertical deflection circuit if the display device is, for example, a CRT display device, and to control the drive circuit if it is, for example, a liquid crystal display device.

By the way, since the control of the display is complicated, many of the displays have a built-in microcomputer for built-in equipment, and a counter with a built-in microcomputer is used for both the detection of the synchronizing signal frequency and the effect of cost reduction. It is normal to As a horizontal synchronizing signal frequency detecting circuit using the software of a microcomputer, for example, a horizontal frequency detecting circuit previously applied as Japanese Patent Application No. 9-129511 will be described as prior art.

FIG. 4 is a block diagram of a horizontal frequency detecting circuit as a prior art. In FIG. 4, reference numeral 1 is a control circuit. Reference numeral 2 is an n-ary counter that counts the horizontal synchronizing signal and sets the output to a high level when the count value becomes n. Three
Is an m-ary counter that counts horizontal synchronizing signals and outputs high level when the count value reaches m. Reference numeral 4 is a first latch circuit that holds the output value of the reference clock counter 8 when the output of the n-ary counter 2 becomes high level. Reference numeral 5 is a second latch circuit which holds the output value of the reference clock counter 8 when the output of the m-ary counter 3 becomes high level. 6 is the first and second latch circuits 4,
5 is a differencer that takes the difference between the output values of the reference clock counter 8 held in 5. Reference numeral 7 is a reference clock generation circuit for generating a reference clock having a cycle of T. Reference numeral 8 is a reference clock counter that counts the reference clock and outputs the count value.

The operation of the horizontal frequency detecting circuit having the above configuration will be described below. When the vertical synchronizing signal is input to the control circuit 1, the control circuit 1 simultaneously starts the counting of the n-ary counter 2 and the m-ary counter 3 whose initial values are set to 0. The n-ary counter 2 counts the horizontal synchronizing signal when it is input, and sets the output to the high level when the count value reaches n. As a result, the count value T ₁ of the reference clock counter 8 is latched in the first latch circuit 4. Similarly, the m-ary counter 3 counts the horizontal synchronizing signal when it is input, and sets the output to the high level when the count value reaches m. As a result, the count value T ₂ of the reference clock counter 8 is latched in the second latch circuit 5.

The control circuit 1 calculates F _H = (m−n) / ((T ₂ −T ₁ ) × T) to obtain the frequency F _H of the horizontal synchronizing signal.

[0007]

The configuration shown in FIG. 4 is actually realized by using the built-in peripheral hardware of the microcomputer for embedded equipment and performing control by software. For example, the start of the n-ary counter 2 and the m-ary counter 3 is realized by setting / resetting a start flag assigned to a specific bit of the address of the microcomputer in the interrupt processing program by the vertical synchronizing signal.

However, the start flags of the n-ary counter 2 and the m-ary counter 3 are not necessarily at the same address of the microcomputer, and depending on the configuration of the microcomputer, the n-ary counter 2 and the m-ary counter 3 are started. The instruction of the microcomputer may be divided into two instructions. If the horizontal synchronizing signal is input between the execution of one of these two instructions and the execution of the other instruction, the counting of the horizontal synchronizing signals in the n-ary counter 2 and the m-ary counter 3 will start. There is a problem in that the detection value of the horizontal synchronizing signal frequency is lowered because the count value of the n-ary counter 2 and the count value of the m-ary counter 3 are not synchronized at the same time.

Therefore, an object of the present invention is to enable horizontal synchronization signal frequencies in the first and second counters to start at the same time and to detect the horizontal synchronization signal frequency with high accuracy. A detection method and a horizontal synchronization signal frequency detection circuit are provided. Another object of the present invention is to provide a low-cost horizontal sync signal frequency detection circuit that does not require hardware changes, only software changes.

[0010]

In order to solve the above problems, according to the present invention, the first and second counters, which are set to the same initial value and respectively count horizontal synchronizing signals, start counting, The count value b of the free running counter of the clock cycle T _f when the count value of the first counter reaches a is taken in, and the count value of the free running counter when the count value of the second counter reaches (a + m) When the frequency f _H of the horizontal synchronizing signal is obtained by taking in (b + n) and calculating f _H = m / (n × T _f ), the counting of the first and second counters for counting the horizontal synchronizing signal is started. After that, the count values of the first and second counters are respectively captured and compared, and the first and second counters are counted until the count values of the first and second counters match. By setting the initial value in the counter, starting the counting of the first and second counters, and fetching and comparing the count values of the first and second counters, the first and second counters are simultaneously leveled. The counting of the synchronization signal can be started.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A horizontal synchronizing signal frequency detecting method according to claim 1 of the present invention is to start counting of first and second counters which are set to the same initial value and count horizontal synchronizing signals respectively. , The count value b of the free running counter of the clock cycle T _f when the count value of the first counter reaches a, and the count value of the free running counter when the count value of the second counter reaches (a + m) When the frequency f _H of the horizontal synchronizing signal is obtained by taking in the count value (b + n) and calculating f _H = m / (n × T _f ), after the counting of the first and second counters is started, The count values of the first and second counters are respectively fetched and compared, and the initial values of the first and second counters are kept until the count values of the first and second counters match. And repeating the capture and comparison of the constant and the count value of the start and the first and second counter counting the first and second counters.

According to this method, after the counting of the first and second counters is started, the count values of the first and second counters are respectively fetched and compared, and the first
And the first value until the count values of the second counter match.
Setting initial values in the first and second counters and starting counting of the first and second counters and the first and second counters
When the count value of the counter is repeatedly fetched and compared, the horizontal sync signal is input between the start of counting the horizontal sync signal of the first counter and the start of counting the horizontal sync signal of the second counter. In this case, since the count values of the first and second counters are different, the initial value setting and start of the first and second counters are performed again, which is the count values of the first and second counters. Will be repeated until
The counting of the horizontal synchronizing signals in the first and second counters can be started at the same time, and the horizontal synchronizing signal frequency can be detected with high accuracy.

A horizontal synchronizing signal frequency detecting method according to a second aspect of the present invention is the horizontal synchronizing signal frequency detecting method according to the first aspect, wherein the count values of the first and second counters are fetched in the first and the second order. It is characterized in that the starting order of counting by the second counter is reversed. According to this method, if the order of capturing the count values of the first and second counters is reversed from the order of starting the counts of the first and second counters, this order is the same as that of the counts of the first and second counters. The difference at the time of start is increased instead of being canceled, and when the horizontal synchronization signal is input between the acquisition of the count value of the first counter and the acquisition of the count value of the second counter, the first and second counters It is possible to avoid the problem that it cannot be detected that the horizontal synchronizing signal has been input during the start of counting, and it is possible to ensure highly accurate detection of the horizontal synchronizing signal frequency.

According to the third aspect of the present invention, the horizontal synchronizing signal frequency detecting circuit counts at the clock cycle T _f and the first and second counters which are set to the same initial value and count the horizontal synchronizing signals respectively. A free running counter,
The counting of the first and second counters is started, and the first
The count value b of the free running counter when the count value of the counter reaches a, and the count value (b + n) of the free running counter when the count value of the second counter reaches (a + m), and a calculation control means for calculating the frequency f _H of the horizontal synchronizing signal by calculating f _H = m / (n × T _f ).

Further, in addition to the above-mentioned function, the arithmetic control means starts the counting of the first and second counters, then fetches the count values of the first and second counters and compares them, respectively. Until the count values of the first and second counters match, the initial values are set in the first and second counters, the counting of the first and second counters is started, and the count values of the first and second counters are set. A function to repeat capturing and comparing is added.

According to this structure, after the counting of the first and second counters is started, the count values of the first and second counters are respectively fetched and compared, and the first
And the first value until the count values of the second counter match.
Setting initial values in the first and second counters and starting counting of the first and second counters and the first and second counters
When the count value of the counter is fetched and compared repeatedly, the horizontal sync signal is input between the start of counting the horizontal sync signal of the first counter and the start of counting the horizontal sync signal of the second counter. In this case, since the count values of the first and second counters are different, the initial value setting and start of the first and second counters are performed again, which is the count values of the first and second counters. Will be repeated until
The counting of the horizontal synchronizing signals in the first and second counters can be started at the same time, and the horizontal synchronizing signal frequency can be detected with high accuracy.

A horizontal synchronizing signal frequency detecting circuit according to a fourth aspect of the present invention is characterized in that, in the horizontal synchronizing signal frequency detecting circuit according to the third aspect, the arithmetic control means comprises a microcomputer. According to this configuration, since the arithmetic and control unit is configured by the microcomputer, only by changing the software of the microcomputer,
The horizontal synchronizing signal frequency can be detected with high accuracy without changing the hardware, and the cost can be kept low.

A horizontal synchronizing signal frequency detecting circuit according to a fifth aspect of the present invention is the horizontal synchronizing signal frequency detecting circuit according to the third or fourth aspect, in which the count values of the first and second counters are fetched in the first order. And the order of starting the counting of the second counter is reversed. According to this configuration, when the order in which the count values of the first and second counters are fetched is opposite to the order of starting the counts of the first and second counters, this order is the same as the counts of the first and second counters. The difference at the time of start is increased instead of being canceled, and when the horizontal synchronization signal is input between the acquisition of the count value of the first counter and the acquisition of the count value of the second counter, the first and second counters It is possible to avoid the problem that it cannot be detected that the horizontal synchronizing signal has been input during the start of counting, and it is possible to ensure highly accurate detection of the horizontal synchronizing signal frequency.

A horizontal synchronizing signal frequency detecting method and a horizontal synchronizing signal frequency detecting circuit according to an embodiment of the present invention will be described below with reference to FIGS. 1, 2 and 3.
FIG. 1 is a flow chart showing the contents of the processing for simultaneously starting the counting of horizontal synchronizing signals in the first and second counters in the embodiment of the present invention. FIG. 2 is a block diagram showing an example of the hardware configuration of a microcomputer as a typical arithmetic control unit for performing the processing of the flowchart of FIG. 1, that is, an example of the configuration of the horizontal synchronizing signal frequency detecting circuit of the present invention.

First, in FIG. 2, reference numeral 1 is a first counter for outputting an input capture trigger signal 11 when a horizontal synchronizing signal is counted by setting 0 as an initial value. Reference numeral 2 is a second counter which is set to the same initial value as that of the first counter 1 and outputs the input capture trigger signal 12 when (a + m) horizontal synchronizing signals are counted. Reference numeral 3 is a free running counter that counts at the clock cycle T _f .

Reference numeral 4 denotes a first input capture generally mounted on an embedded microcomputer, the operation of which is an input capture trigger signal 11 output when the count value of the first counter 1 reaches a. In response to the above, it has a function of fetching and holding the count value of the free running counter 3. Reference numeral 5 is a second input capture generally mounted in the built-in microcomputer, and its operation is the input capture trigger signal 12 output when the count value of the second counter 2 reaches (a + m). In response to, the input capture is for capturing and holding the count value of the free running counter 3.

Reference numeral 6 denotes a CPU of the microcomputer, which starts the first and second counters 1 and 2 and counts the count value b of the free running counter 3 which is the data held by the first and second input captures 4 and 5. (B + n) is taken in, and the function of obtaining the frequency f _H of the horizontal synchronizing signal by the calculation of f _H = m / (n × T _f ) is provided, and the counting of the first and second counters 1 and 2 is started. The first and second counters 1,
The two count values are respectively fetched and compared, and the initial values are set (reset) to the first and second counters 1 and 2 and the first counters 1 and 2 until the count values of the first and second counters 1 and 2 match. It also has a function of repeating the count start of the second counters 1 and 2 and the fetching and comparison of the count values of the first and second counters 1 and 2.

Next, in FIG. 1, 10 indicates the start of the flow chart, which is usually a vertical synchronizing signal interrupt. In some cases, such as when there is no vertical sync signal, a timer interrupt may be used. In this embodiment, the starting factor is not particularly limited, and the position of the processing to be started does not matter. The fact that the position of the process to be started does not matter has the following meaning. That is, the vertical sync signal interrupt is used for various purposes, and is also used for other than the horizontal sync signal frequency detection. In order to realize the present invention, it means that the content of the interrupt process which is the starting factor does not have to be occupied only by the process of the present invention.

Reference numeral 20 is a step for starting the first counter 1 in FIG. In this step, processing (reset processing or preset processing) for setting the initial value of the first count 1 to 0, for example, is also performed. 30 is a step for starting the second counter 2 in FIG. In this step, the initial value of the first count 1 is set to 0, for example.
The process of setting (reset process or preset process) is also performed.

Reference numeral 40 is a step of fetching (reading) the count value of the second counter 1 of FIG. Reference numeral 50 is a step of fetching (reading) the count value of the first counter 2 of FIG. 60 is a step of comparing the count values of both the first counter 1 and the second counter 2 fetched in steps 40 and 50, and the count values of the first and second counters 1 and 2 are determined based on the comparison result. If they are different, the control is transferred before step 20 and the operation from the switch 20 is repeated. If they match, the next control is performed.

Reference numeral 70 means the end of this control. Of course, other processing may be performed after this. 3 (a), 3 (b)
In addition, the input capture trigger signal 1 described in FIG.
The output waveforms of 1 and 12 are shown. 7A shows the waveform of the input capture trigger signal 11, and FIG. 7B shows the waveform of the input capture trigger signal 12. Figure 3
The time t ₁ in the middle is the time when the first counter 1 and the second counter 2 start counting.

Further, time t ₂ is the time when the first counter 1 counts a number of horizontal synchronizing signals. The count value of the free running counter 3 input-captured at that time is set to b. Further, time t ₃ is the time when the second counter 2 counts (a + m) horizontal synchronizing signals. The count value of the free running counter 3 input-captured at that time is (b + n).

Based on these data, the CPU 6 obtains the frequency f _H of the horizontal synchronizing signal according to the arithmetic expression of f _H = m (n × T _f ). Here, an important point is to accurately cut out the period of m horizontal sync signals. The accuracy of this cutout is related to the frequency detection accuracy. Mainly, this accuracy depends on the first counter 1 and the second counter.
It is caused by the error in the count start time of the counter 2. In order to improve this, the control according to the flowchart of FIG. 1 is performed at time t ₁ in FIG.

In the flowchart of FIG. 1, after the first counter 1 starts counting horizontal synchronizing signals in step 20, the second counter 2 starts counting horizontal synchronizing signals in step 30. This makes the first
The horizontal synchronizing signals are respectively counted by the counter 1 and the second counter 2 in step 20 and step 3.
If the horizontal synchronizing signal is counted between 0 and 0, an error occurs in the above-mentioned cutout period.

When the above error occurs, it is identified by the subsequent step 60. In Step 60, Steps 40 and 50
The count value of the first counter 1 and the count value of the second counter 2 fetched in step 2 are compared. If step 2
If there is a horizontal sync signal between 0 and step 30,
Since the count value of the first counter 1 and the count value of the second counter 2 do not match, the process returns to step 20 and the subsequent processes are repeated.

If the count value of the first counter 1 and the count value of the second counter 2 match, step 20
Since it means that the horizontal synchronizing signal is not input between step 30 and step 30, it means that the simultaneous counting of the horizontal synchronizing signals in the first counter 1 and the second counter 2 is realized. Achieve the purpose. Since the instruction of the microcomputer is sufficiently high with respect to the rate of the horizontal synchronizing signal, normally two horizontal synchronizing signals are transmitted between the first counter 1 and the second counter 2 between step 20 and step 50. Will not be counted by. However, when multiple interrupts are allowed, the period from step 20 to step 50 becomes long, and two horizontal synchronization signals may be counted, so caution is required in mounting.

Hereinafter, this point will be specifically described.
For example, it is assumed that the horizontal synchronizing signal is counted immediately after the first counter 1 is started in step 20. Then, in step 30, the second counter 2 starts counting. At this point, the count value of the first counter 1 is 1,
The count value of the second counter 2 is 0. Essentially this should be detected in step 60.

However, after reading the count value of the first counter 1 in step 40 and before reading the count value of the second counter 2 in step 50, the horizontal synchronizing signal is input again. In this case, the count value of the first counter 1 remains 1, but the count value of the second counter 2 changes from 0 to 1. Therefore, at the time of comparison in step 60, the count values of the first and second counters 1 and 2 match, and no malfunction is detected.

As a countermeasure in this case, it is sufficient to ensure that the execution time of each step (the time required to execute from step 20 to step 50) is faster than the rate of the horizontal synchronizing signal. Even if the above time guarantee is not performed, the above malfunction can be prevented by the following configuration. That is, the above-described malfunction causes the order of steps 40 and 50 to be reversed as preprocessing for comparing the count values in step 60, and the reading of the count value of the second counter 2 in step 50 is performed in step 40. The problem is solved by reading the count value of the first counter 1 of 1. More generally, it means that the order of starting the counter and the order of reading the value of the counter may be reversed.

The above problem will be described in the case where the count value of the first counter 1 is 1 and the count value of the second counter 2 is 0 after step 30 in the above example. In this case, the second in step 50
If the counter 2 is read first and the first counter 1 in step 40 is read later, when the horizontal synchronization signal is counted between step 50 and step 40, Count value is 2, second
The count value of the counter 2 is 0. Therefore, the result of the comparison is different, and the object of the present invention can be achieved.

According to this embodiment, the first and second
After starting the counting of the counters 1 and 2, the count values of the first and second counters 1 and 2 are respectively fetched and compared, and until the count values of the first and second counters 1 and 2 match. First and second counters 1, 2
Since the setting of the initial value to the first counter and the start of counting of the first and second counters 1 and 2 and the fetching and comparison of the count values of the first and second counters 1 and 2 are repeated, When the horizontal synchronizing signal is input between the start of counting the horizontal synchronizing signal and the start of counting the horizontal synchronizing signal of the second counter 2, the count values of the first and second counters 1 and 2 are different. Therefore, the initial value setting and the start of the first and second counters 1 and 2 are performed again, which is the first value.
And the second counters 1 and 2 are repeated until the count values of the first and second counters 1 and 2 match.
It is possible to simultaneously start the counting of the horizontal synchronizing signal in (1), and it is possible to detect the horizontal synchronizing signal frequency with high accuracy.

Further, the software of the microcomputer controls the first and second counters 1 and 2, the free running counter 3, the first and second input captures 4 and 5, and finds the frequency f _H of the horizontal synchronizing signal. Since it is configured to perform calculations, it is possible to detect the horizontal sync signal frequency with high accuracy without changing the hardware by simply changing the software of the microcomputer from the conventional example, and to keep the cost down. be able to.

Further, since the order of loading the count values of the first and second counters 1 and 2 is reversed from the order of starting the counting of the first and second counters 1 and 2, this order is the first and the second. Instead of canceling the difference at the start of counting of the counters 1 and 2,
When a horizontal synchronization signal is input between the capture of the count value of the first counter 1 and the capture of the count value of the second counter 2, the horizontal synchronization signal is input between the start of counting of the first and second counters 1 and 2. It is possible to avoid the problem that it is not possible to detect the occurrence of the error, and it is possible to ensure highly accurate detection of the horizontal synchronizing signal frequency.

In the flow chart of FIG. 1, the first counter 1 is started and then the second counter 2 is started, but the order may be reversed.

[0040]

According to the horizontal synchronizing signal frequency detecting method of the first aspect of the present invention, the counting of the horizontal synchronizing signals in the first and second counters can be started at the same time, and the horizontal synchronizing signal frequency can be increased. It becomes possible to detect with high accuracy. Further, according to the horizontal synchronizing signal frequency detecting method of the second aspect of the present invention, it becomes possible to ensure the highly accurate detection of the horizontal synchronizing signal frequency.

Further, according to the horizontal synchronizing signal frequency detecting circuit of the third aspect of the present invention, the counting of the horizontal synchronizing signals in the first and second counters can be simultaneously started, and the horizontal synchronizing signal frequency can be increased. It becomes possible to detect with high accuracy. According to the horizontal synchronizing signal frequency detecting circuit of the fourth aspect of the present invention, it is possible to detect the horizontal synchronizing signal frequency with high accuracy by changing the software of the microcomputer without changing the hardware. Therefore, the cost can be kept low.

According to the horizontal synchronizing signal frequency detecting circuit of the fifth aspect of the present invention, it is possible to ensure the detection of the horizontal synchronizing signal frequency with high accuracy.

[Brief description of drawings]

FIG. 1 shows the contents of processing for simultaneously starting the counting of horizontal synchronizing signals by the first and second counters in the embodiment of the horizontal synchronizing signal frequency detecting method and the horizontal synchronizing signal frequency detecting circuit of the present invention. It is a flowchart.

FIG. 2 is a block diagram of an exemplary microcomputer when using the flowchart of FIG.

FIG. 3 is an output waveform diagram of an input capture trigger signal.

FIG. 4 is a block diagram of a conventional horizontal frequency detection circuit.

[Explanation of symbols]

1 first counter 2 Second counter 3 free running counter 4 First input capture 5 Second input capture 6 CPU 11 Input capture trigger signal 12 Input capture trigger signal

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Claims (5)

(57) [Claims] 1. A clock cycle when the first and second counters, which are set to the same initial value and respectively count horizontal synchronizing signals, start counting and the count value of the first counter reaches a. The count value b of the free running counter of T _f is fetched, and the count value (b + n) of the free running counter when the count value of the second counter reaches (a + m) is fetched, and f _H = m / (n × a horizontal sync signal frequency detection method by calculating the T _f) determining the frequency f _H of the horizontal synchronizing signal, the after starting the counting of the first and second counter, said first and second The count values of the counters are respectively fetched and compared, and initial values to the first and second counters are obtained until the count values of the first and second counters match. And the start of counting of the first and second counters and the fetching and comparison of the count values of the first and second counters are repeated. 2. The horizontal synchronizing signal frequency according to claim 1, wherein the order of taking in the count values of the first and second counters is reversed from the order of starting the counting of the first and second counters. Detection method. 3. A first and a second counter which are set to the same initial value and count horizontal synchronizing signals respectively, a free running counter which counts at a clock cycle T _f , and the first and second counters. Start counting,
The count value b of the free running counter when the count value of the first counter reaches a is taken in,
When the count value of the second counter reaches (a + m), the count value of the free running counter (b +
n), and a horizontal sync signal frequency detection circuit comprising: arithmetic control means for obtaining the frequency f _H of the horizontal sync signal by calculating f _H = m / (n × T _f ). After starting the counting of the second counter, the count values of the first and second counters are respectively fetched and compared, and the first and second counters are counted until the count values of the first and second counters match. A function for repeating the setting of an initial value to the counter, the start of counting by the first and second counters, and the capturing and comparison of the count values by the first and second counters are added to the arithmetic control means. Horizontal synchronization signal frequency detection circuit characterized by. 4. The horizontal synchronizing signal frequency detecting circuit according to claim 3, wherein the arithmetic control means comprises a microcomputer. 5. The horizontal synchronization according to claim 3, wherein the order of taking in the count values of the first and second counters is reversed from the order of starting the counting of the first and second counters. Signal frequency detection circuit.