JP3399450B2 - Frequency detection method and frequency detection circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronizing signal frequency detecting method suitable for software of a microcomputer such as a multi-scan monitor or a liquid crystal display monitor. The present invention also relates to a remote control pulse period detection method suitable for software of a microcomputer such as a multi-scan monitor or a liquid crystal display monitor.

[0002]

2. Description of the Related Art In various types of computer equipment connected to a multi-scan display, the frequencies of the horizontal synchronizing signal and the vertical synchronizing signal of the video signal output to the display are often different.

Therefore, in the multi-scan display, in order to display the data from the computer device connected thereto, the frequencies of the horizontal synchronizing signal and the vertical synchronizing signal are detected with high accuracy, and the detected horizontal and vertical synchronizing signals are detected. If the display, which is a display device, follows each frequency, for example, if it is a cathode ray tube (hereinafter referred to as CRT), it is necessary to control horizontal and vertical deflection circuits, for example, if it is a liquid crystal, it is necessary to control a drive circuit.

Moreover, is usual that are performed using the detected counter of the microcomputer built doubles the effect of the cost of the display is large and the synchronization signal frequency in recent years that a microcomputer for an embedded device . These microcomputers have a built-in counter that counts a reference clock signal and a register that latches the value of the counter, and synchronizes the value of the counter with the rising or falling of the input signal. The function to latch in the built-in register is built in. This latch function is generally called input capture. As a method of detecting the signal frequency, for example, assuming that a value obtained by capturing the counter value at the rising edge of the signal is A and a value captured at the next rising edge is B as shown in FIG.
-Determined by A. The frequency can be detected from the cycle thus obtained.

On the other hand, in a computer display, the frequency of an input synchronizing signal increases, and in the standard of high resolution display called UXGA, horizontal 1
It must be possible to detect sync frequencies of 10 kHz or more and 90 Hz or more in the vertical direction. Furthermore, the lower limit is VESA (Vi
deo Electronics Standards Association: an industry group of graphics device manufacturers for personal computers) DPMS
(Display Power Management Signaling: a standard related to display power management) specifies that 10 Hz or less is a non-signal, so it must be able to detect up to 10 Hz or less.

Further, in order to perform multi-scan on a liquid crystal display which has become widespread in recent years, highly accurate input signal frequency (cycle) information is required for resolution conversion. Thus, as an example in which high-precision input signal frequency detection and wide-range input signal detection are realized using software of a microcomputer, for example, Japanese Patent Laid-Open No. 2000-1313.
The frequency detection method described in Japanese Patent No. 55 is known.

In this example, in order to detect the frequency in a wide range and with high accuracy, the bit extension of the counter is performed by software using an overflow interrupt. At that time, the order of interrupt processing at the time of signal input (input capture interrupt) and overflow interrupt processing in the CPU may be reversed depending on the priority order of the interrupt processing. Therefore, measures for that are proposed. The description will be given below.

FIG. 5 is a timing chart showing the order of occurrence of two interrupt processes (input interrupt process and overflow interrupt) and the order in which the processes are interchanged.
Assuming that the counter is 16 bits, normally, when the counter value changes from "FFFFh" to "0000h",
Overflow interrupt occurs. By the overflow interrupt process, the soft counter of the memory is incremented, for example, from "A" to "A + 1".

However, when the falling edge of the input signal 8 such as the synchronizing signal arrives within the delay time for performing the overflow interrupt processing, the input may be received and the input interrupt processing may be processed first. In this case, since the software counter is originally incremented to "A + 1" by the overflow interrupt process, the interrupt process is performed before that. Therefore, the value of the software counter is processed as "A" before the increment. Will be done.

FIG. 6 is a flowchart showing a solution to the problem. FIG. 6A shows the processing of an overflow interrupt that occurs when the counter 3 overflows. In the flowchart of FIG. 6A, step 31 is a step of checking whether or not there is a synchronization signal interrupt request and branching according to the result. Step 32 is a process of setting a collision flag which secures an area on the memory. If there is an input signal interrupt processing request during the overflow interrupt processing, it can be considered that a collision has occurred between the overflow interrupt processing and the input signal interrupt processing.

On the other hand, if there is no input signal interrupt processing request, step 33 is performed. FIG. 6B shows the processing of an input signal interrupt that occurs when a signal is input. In the flowchart of FIG. 6B, step 35 is a step of confirming the collision flag set in FIG. 6A and branching according to the result. When the collision flag is set, the variable "A_HIGH" of the soft counter on the memory has not been incremented, so it is incremented during the processing of this signal interrupt.

After the collision flag is cleared in step 36, it is checked whether or not the value of the counter when the input signal is detected in step 37 (hereinafter referred to as the input capture value) is less than or equal to a specific value "B". The result is branched. That is, for example, when the counter 3 that performs input capture has 16 bits, the specific value “B” is used as an example and the intermediate value “FFFFh” of the counter 3 is used.
By setting "/ 2 = 7FFFh", it is possible to determine that the signal is input before the overflow if the input capture value is larger than "7FFFh", and it is possible to determine that the signal is input after the overflow if the input capture value is smaller than "7FFFh".

Therefore, if the result of step 37 is "no", step 38 may be performed first and then step 33, and if "yes", step 33 may be performed first and then step 38 is performed. You can do it later.

As described above, when a collision between the overflow interrupt processing and the input signal interrupt processing is detected by the overflow interrupt processing, the collision flag is set and the collision flag is set during the input signal interrupt processing. after verifying that the collision from the input capture value is determined before or after the overflow, high accuracy without depending on an interrupt occurrence order, and it is possible to achieve a wide range of peripheral <br/> wavenumber detecting device .

[0015]

In the recent era of multimedia, the input sources of computer displays have come to support not only computer signals but also various signals such as AV signals. For example, when the child screen function is installed, it is necessary to detect the synchronization signal over a wide range with high accuracy, and at the same time, it is necessary to detect a plurality of systems. Furthermore, if the remote control is enabled, it is necessary to measure the remote control pulse at the same time.

[0016] However, in the conventional method, be sure to Input
For door capture input was necessary, at the same time frequency
The input of the least number of inputs of the input capture of the microcomputer when attempting detection of input only a single microcomputer there is a problem that can not be handled.

Further, there is a problem that input capture is necessary even for an input that requires relatively low detection accuracy such as remote control pulse reception.

In view of such a problem, the present invention does not need to change the counter, which is the built-in hardware of the microcomputer, has a high accuracy when the frequency detection of a wide range is provided at a low cost and has a high accuracy even when there is no input capture function. It is an object of the present invention to provide a frequency detection method that can be performed with the accuracy of the level of the embedded processing time.

[0019]

In order to solve the above-mentioned problems, the frequency detection method of the present invention is the number of overflows of the counter calculated using overflow interrupt processing which occurs when the counter operating in a predetermined cycle overflows. When, the measured input using the value of the counter
A frequency detection method characterized by detecting the period of the signal , the second overflow number of the counter calculated by the interrupt processing generated in a phase different from the overflow interrupt processing of the counter, and the The frequency detection method is characterized in that the number of overflows is switched depending on the input timing of the measured input signal to detect the period.

According to the above invention, the bit length of the counter is not limited even if the input capture value at the time of detecting the input signal is not particularly used, and the counter which is the built-in hardware of the microcomputer does not need to be changed. It is possible to detect a wide range of frequencies at a cost, and it is possible to provide a frequency detection method that can be realized with high accuracy by using an input capture value.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) FIG. 1 is a block diagram showing a basic structure for realizing a frequency detecting method of the present invention. In FIG. 1, 1
Is a microcomputer for built-in equipment, and has a built-in counter 3. 2 is a reference clock generator. Three
Is a counter that receives the clock output from the reference clock generator 2 and counts the clock. Reference numeral 8 is a measured input signal (hereinafter referred to as an input signal). 4 issues an interrupt processing request to the CPU 5 described later by an arbitrary falling edge or rising edge of the input signal 8,
Further, it is an interrupt processing accepting means for performing scheduling such as a priority order for other interrupt processing requests that have occurred and for generating interrupt requests to the CPU 5.

Reference numeral 5 denotes a central processing unit (hereinafter referred to as CPU) that receives data and programs from each block connected to a BUS 7 described later and performs arithmetic processing. 6
Is a randomly accessible memory. Reference numeral 7 is a BUS including data, addresses and control signals.

The first embodiment of the present invention will be described below with reference to FIGS. 2 and 3. FIG. 2 is a flowchart in this embodiment. 2A is a flowchart of overflow interrupt processing, and FIG. 2B is a flowchart of a timer interrupt for generating an interrupt with an arbitrary value of the counter. The point of the embodiment of the present invention is that the number of overflows of the counter 3 is counted by two counters, a soft counter A and a soft counter B having different phases.

FIG. 3 is a timing chart for explaining the operation of this embodiment. In FIG. 3, soft counter A and soft counter B are variables whose areas are secured in the RAM of the microcomputer 1. The above variable will be described as 16 bits.

The point of the present invention is to count the number of overflows of the counter 3 by two counters, a soft counter A and a soft counter B having different phases.

In order to realize the two-phase soft counter, in step 50 of FIG. 2, when the counter 3 overflows, the soft counter A is incremented (incremented).

Similarly, when the counter 3 changes from the intermediate value "7FFFh" to "8000h", for example, as shown in FIG.
When the timer interrupt process of (b) is generated, the soft counter B shown in FIG. 3 is counted up in step 51, and two soft counters having 180 ° different phases can be obtained.

On the other hand, when the input signal 8 is inputted, which of the two soft counters A and B is used to measure the time is determined by the value of the counter 3 at the time of the input during the interruption of the input signal.

In FIG. 3, the value of the counter 3 is "FFF.
When an input signal is input in the vicinity of "Fh" and "0000h", the soft counter B is used because the order of overflow interrupt processing and input signal interrupt processing may be reversed. In that case, since the value of the soft counter B is not incremented for a while, the value of the soft counter value B is not affected even when the input signal interrupt process and the overflow interrupt process of the counter 3 are mixed . Since the phase shift must be corrected when using the soft counter B, the value of the counter 3 is "8".
When it is 000h or more, it is handled by adding "-1" to the value. This process is performed by step 53 and step 5 in FIG.
Equivalent to 5.

The value of the counter 3 is "7FFFh",
The soft counter A is used because it is possible that the order of the timer interrupt processing and the input signal interrupt processing may be reversed in the vicinity of "8000h".

In the above description, the ambiguous word "near" is used, but as a concrete example, as shown in FIG. 3, for example, a section (section) where the value of the counter 3 is from "C000h" to "3FFFh" is the soft counter B is used. B) and select "400
The section from 0h ”to“ BFFFh ”may be the section where the soft counter A is used (section A). Since the switching section can be set sufficiently wide in this manner, the cycle can be measured even if the value of the counter 3 at the time of accurate signal input is unknown.
The above process is performed in step 52 of FIG.

As described above, in the present embodiment, two software counters for expanding the upper bits of the counter 3 are prepared with different phases, and an interrupt for bit expansion and an interrupt for frequency measurement are provided. Bit extension of the counter is possible by switching so as to avoid a section in which the two interrupt generation orders and the interrupt processing order may be interchanged.

Further, since the section can be switched over a wide range, the counter value can be captured by the software by the normal interrupt processing without the capture of the counter value by the input capture, and the resources of the microcomputer can be made effective. It can be used. Although the counter value is 16 bits and the software counters A and B are 16 bits in this embodiment, it is needless to say that they are not limited thereto.

Further, although the overflow interrupt is used in the present embodiment, it goes without saying that the same effect can be obtained by using the interrupt generated when the counter 3 reaches a predetermined value.

In this embodiment, the soft counter B is generated when the counter 3 changes from "7FFFh" to "8000h", but it goes without saying that another value may be used.

In this embodiment, the section B for switching between the two soft counters is set to "C000h" to "3FFF."
h ”and the section A is set to“ 4000h ”to“ BFFFh ”, but it goes without saying that other ranges may be used if the interrupt processing time, interrupt delay time, etc. are taken into consideration.

[0037]

According to the present invention, a wide range of frequency detection can be performed at a low cost without being restricted by the bit length of the counter without particularly using the input capture and without changing the counter which is the hardware built into the microcomputer. Further, it is possible to provide a frequency detection method that can be realized with high accuracy by using input capture.

Further, by using an ordinary interrupt input terminal, external pulse measurement such as remote control pulse measurement can be performed without degrading the synchronization signal frequency detection performance.

Even if the order of occurrence of two events of overflow and signal input and the order of corresponding interrupt processing are different depending on the priority order of the interrupts used to realize the above-mentioned effect, the detection result of the signal frequency is not correct. The advantageous effect of providing a frequency detection method that does not occur is obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a basic configuration for realizing a frequency detection method of the present invention.

FIG. 2 is a flowchart in the present embodiment.

FIG. 3 is a timing chart for explaining the operation of the present embodiment.

FIG. 4 is a conceptual diagram of a frequency detection method by software using a microcomputer.

FIG. 5 is a timing chart showing a state in which the generation order and the processing order of two interrupts are exchanged.

FIG. 6 is a flowchart of a conventional frequency detection method.

[Explanation of symbols]

1 microcomputer 2 Reference clock generator 3 counter 4 Interrupt acceptance means 5 CPU 6 memory 7 BUS 8 input signals

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Claims (2)

(57) [Claims] 1. The number of overflows of the counter calculated using overflow interrupt processing that occurs when the counter operating in a predetermined cycle overflows,
A frequency detection method characterized by detecting the period of an input signal under test using the value of the counter, wherein the counter is calculated by an interrupt process generated at a phase different from that of the overflow interrupt of the counter. A frequency detecting method characterized in that the cycle is detected by switching between a second overflow frequency of the counter and the overflow frequency according to the input timing of the measured input signal . 2. A microcomputer having a counter and a software for the microcomputer, a process of counting up a variable by an overflow interrupt of the counter, and an interrupt process generated when an input signal to be measured is input. In the frequency detection circuit, the variable is used as upper data, and the value of the counter at the time of input is used as lower data to perform signal frequency detection. Of the second variable that is counted up by the interrupt process of (1), the value of the variable and the value of the second variable according to the input timing of the measured input signal, and the selecting means of the selecting means. A frequency comprising a calculation means for calculating the frequency of the input signal from the result and the value of the counter. Out circuit.