JP2002368813A - Delay time distribution measurement device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem that a processing load is increased resulting in making the device configuration complicated because of writing of transmission time to test packet data and calculation of delay time distribution or the like through software processing in a conventional delay time distribution measurement device. SOLUTION: A transmission circuit 12 outputs a start signal to a counter 15 at the same time when the circuit 12 transmits test packet data to a system 2, an extract circuit 14 extracts the test packet data passing through the system 2 and outputs a stop signal to the counter 15 at the same time, the counter 15 accesses a distribution memory 16 by using a count of delay times counted from reception of the start signal until the reception of the stop signal for an address, the distribution memory 16 outputs memory data 16A stored in the accessed address to an adder circuit 17, and the adder circuit 17 counts up the frequency of the memory data 16A by one and writes the result to the address.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay time distribution measuring device for measuring a delay time distribution of data in a system on a data line (communication line).

[0002]

2. Description of the Related Art Packet data transmitted on a data line (communication line) is delayed when passing through a system such as an exchange provided on the data line. The delay time of packet data in such a system (the time from when the packet data is input to the system until it is output) is a parameter indicating the performance of the system, but the delay time when passing through the system is not constant. Therefore, it is necessary to measure the distribution of the delay time of the packet data in order to know the range of the delay time.

In a conventional delay time distribution measuring device, a transmission time is written into one test packet data, the test packet data is transmitted to a test target (measurement target) system, and the test packet data passing through the system is transmitted. Is extracted, and the extraction time is measured. Then, in the conventional delay time distribution measuring device, the delay time of the system is obtained from the transmission time written in the test packet data and the extraction time of the test packet data, and the delay time is written in the memory as it is.

The conventional delay time distribution measuring device repeats the above operation several times in order to obtain the delay time distribution of the system, and sequentially writes the delay times obtained as a result in a memory. In the conventional delay time distribution measuring device,
A processor in the control device reads out the data of the delay time written in the memory and performs software processing to obtain the distribution of the delay time of the system.

[0005]

However, in the conventional delay time distribution measuring device, as described above, the transmission time is written to the test packet data and transmitted to the system.
Since the delay time is calculated from the transmission time and the extraction time of the test packet data and the delay time is written in the memory, the processing load of the work of writing the transmission time and the work of writing the delay time is increased. In particular, in order to measure the distribution of the delay time of the system, it is necessary to sample data of several delay times, so that such a writing operation must be performed many times, and the processing load becomes excessive. Would.

In the conventional delay time distribution measuring device,
As described above, since the processor in the control device calculates the distribution of the delay time by software processing based on the data of the plurality of delay times written in the memory, such a processing load is large, and It is necessary to incorporate a processor and software (program) for calculating the distribution of delay times in the processor, which leads to a complicated device configuration and an increase in cost.

In the conventional delay time distribution measuring device,
As described above, the processing load is increased by writing the transmission time to the test packet data and calculating the delay time distribution by software processing. Therefore, it is necessary to measure the delay time distribution by high-speed processing. Could not.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and can reduce the processing load and can obtain (measure) the delay time distribution at high speed. The aim is to obtain a measuring device.

Another object of the present invention is to provide a delay time distribution measuring device which can be realized only with a simple hardware configuration and can suppress a complicated device configuration and an increase in cost.

[0010]

In order to achieve the above object, the present invention provides a test packet data generator for generating test packet data and a test packet data generated by the test packet data generator for a system. A transmitting unit for transmitting and outputting a start signal at the same time as transmitting the test packet data; an extracting unit for extracting test packet data having passed through the system and outputting a stop signal at the same time as extracting the test packet data; The counter starts counting when a start signal output from the extraction unit is received, stops counting when a stop signal output from the extraction unit is received, and a counter that accesses the count value of the counted delay time as an address. Outputs the frequency data stored at the accessed address and outputs the frequency data. A storage unit for storing the frequency data counted up or down by one in an address, and an arithmetic unit for counting up or counting down the frequency data output from the storage unit by one and writing the data to the address of the storage unit. It is a thing.

Further, the present invention further comprises a setting unit for setting an interval at which the transmitting unit transmits the test packet data and the number of test packet data transmitted at one start.

Further, the present invention further comprises a setting unit for setting an interval at which the test packet data generation unit generates test packet data and a generation number of test packet data generated by one start.

The present invention further comprises a control unit for reading out frequency data for each delay time stored in the storage unit and outputting the data to the outside.

Further, according to the present invention, the transmitting section selects packet data and test packet data transmitted from the data line to the system and transmits them to the system, and the extracting section identifies and extracts the packet data and the test packet data. It is something to do.

Further, in the present invention, the transmitting section transmits the test packet data to the system at a timing at which the test packet data can be transmitted.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. FIG. 1 is a block diagram showing a delay time distribution measuring device according to the present invention. In FIG. 1, a data line 1 is a communication line for transmitting packet data.
Is the test target (measurement target) of the delay time distribution measurement circuit 10
For example, a packet switch.

The delay time distribution measuring circuit (delay time distribution measuring device) 10 is used to distribute a delay time (time from when the packet data is input to the system 2 to when it is output) when the packet data passes through the system 2. The delay time distribution measurement circuit 10 includes a test packet data generation circuit 11, a transmission interval / transmission number setting circuit 12,
It comprises a sending circuit 13, an extracting circuit 14, a counter 15, a distribution memory 16, an adding circuit 17, and a control circuit 18.

A test packet data generation circuit (test packet data generation unit) 11 generates test (measurement) packet data (hereinafter referred to as test packet data) for measuring the delay time of the packet data in the system 2. Circuit. The transmission circuit (transmission unit) 12 is a circuit that selects and transmits the packet data transmitted from the data line 1 and the test packet data generated by the test packet data generation circuit 11 to the system 2. The sending circuit 12 outputs a reset signal for resetting the count value to the counter 15 before sending the test packet data, and sends a start signal to start counting at the same time as sending the test packet data.
5 is output.

Transmission interval / transmission number setting circuit (setting unit) 13
Is a circuit for setting a unit time interval at which the transmitting circuit 12 transmits test packet data and an arbitrary number of test packet data to be transmitted at one start. For example, the transmission interval of the test packet data is set to 5 seconds, and the transmission number is set to 5. The extraction circuit 14 is a circuit that extracts test packet data that has passed through the system 2 to be tested. The extraction circuit 14 extracts a test packet data and simultaneously outputs a stop signal for stopping the counting to the counter 15.
Output to

The counter 15 is a circuit for counting the delay time required for the test packet data to pass through the system 2. The counter 15 starts counting by a start signal output from the sending circuit 12, stops counting by a stop signal output from the extraction circuit 14, and counts the delay time of the test packet data. Further, as shown in FIG.
The distribution memory 16 is accessed using the count value of the delay time of the test packet data as an address.

The distribution memory (storage unit) 16 is a memory for storing data of delay time distribution of test packet data. As shown in FIG. 2, when the count value is accessed from the counter 15 as an address, the distribution memory 16 outputs the memory data (frequency data) 16A stored at that address to the adder circuit 17, and
The memory data 16A of which the frequency output from the adding circuit 17 is counted up by one is stored at the address.

FIG. 3 is a diagram showing a specific example of memory data (frequency data) stored in the distribution memory. As shown in FIG. 3, the distribution memory 16 has a delay time T as an address, and the memory data 16A stored at that address.
Is defined as a frequency (number of times) Q. That is, the memory data 16A in the distribution memory 16 indicates that the delay time T corresponding to the address has occurred by the frequency Q of the memory data 16A stored in the address. Therefore, by reading the frequency stored in the address corresponding to the delay time T, the user can determine which range the delay time T is in and what value the delay time T has the most. Become.

The addition circuit (arithmetic unit) 17 includes the distribution memory 1
When the memory data 16A output from the memory 6 is received, the frequency of the memory data 16A is counted up (added) by one and written into the distribution memory 16. The control circuit 18 is a circuit that externally reads and writes the memory data 16A of the distribution memory 16 as described above.

Next, the operation will be described. Assuming that the delay time distribution measurement circuit 10 operates, the transmission interval / transmission number setting circuit 13 sets in advance the transmission interval of the test packet data by the transmission circuit 12 and the number of test packet data transmitted by one start. Have been. As described above, for example, it is assumed that the transmission interval of the test packet data is set to 5 seconds and the transmission number is set to 5. Further, it is assumed that the count value of the counter 15 has been reset in advance by a reset signal output from the transmission circuit 12.

When the system 2 is performing packet communication, the transmission circuit 12 selects packet data transmitted from the data line 1 and transmits the packet data to the system 2.

When the delay time distribution measuring circuit 10 starts the process of measuring the delay time distribution of packet data, first, the test packet data generating circuit 11 generates test packet data, and the generated test packet data is generated. The packet data is output to the transmission circuit 12. The transmission circuit 12 performs the test transmitted from the test packet data generation circuit 11 according to the transmission interval and the transmission number of the test packet data set by the transmission interval / transmission number setting circuit 13 and at the timing at which the test packet data can be transmitted. The packet data is selected and transmitted to the system 2.

The transmission circuit 12 operates when the test packet data cannot be transmitted, that is, when the system 2
Is performing packet communication, selects packet data transmitted from the data line 1 and
When the transmission timing is reached, the test packet data is transmitted when the transmission timing is reached.

Here, as described above, when the test packet data transmission interval is set to 5 seconds and the number of transmissions is set to 5, the transmission circuit 12 transmits five test packet data at intervals of 5 seconds to the system 2. To be sent.

The sending circuit 12 selects the test packet data and sends it to the system 2 and, at the same time, outputs a start signal to the counter 15. When receiving the start signal from the transmission circuit 12, the counter 15 starts counting time.

When the test packet data that has passed through the system 2 is input, the extraction circuit 14 identifies and extracts the test packet data. The discrimination between the test packet data by the extraction circuit 14 and the packet data at the time of normal packet communication (that is, the packet data sent from the data line 1 to the system 2) is, for example, 10 packets data.
Bit data, a predetermined bit (for example, the first bit) of the 10-bit packet data
Is determined based on whether is “0” or “1”.

The extraction circuit 14 outputs a stop signal to the counter 15 at the same time as extracting the test packet data. When receiving the stop signal from the extraction circuit 14, the counter 15 stops counting the delay time.

When the counter 15 stops counting,
As shown in FIG. 2, the distribution memory 16 is accessed using the count value as an address. For example, the count value of the counter 15 (the delay time of the test packet data) is 5 ms.
When it is assumed that the address is “5”, the address (number) of “5” in the distribution memory 16 is accessed.

The distribution memory 16 stores the memory data 16 stored at the address accessed from the counter 15.
A is output to the addition circuit 17. In the example of FIG. 3, since the frequency “6” of the memory data 16A is stored at the address “5”, the distribution memory 16 outputs the frequency “6” to the addition circuit 17. The addition circuit 17 includes a distribution memory 16
When the memory data 16A is received from the memory 1, the frequency of the memory data 16A is counted up by one and the distribution memory 1 is counted.
Write to 6. In the example of FIG. 3, since the memory data 16 </ b> A has the frequency “6”, the adder circuit 17 counts up the frequency “6” to “7” and stores the frequency “7” in “5” of the distribution memory 16. Write to the address.

Next, the sending circuit 12 outputs a reset signal to the counter 15 to reset the count value of the counter 15, and the sending interval of the test packet data becomes five.
If it is set to seconds, the test packet data is transmitted to the system 2 5 seconds after the first test packet data is transmitted. The subsequent operation of measuring the delay time distribution is the same as described above.

By repeating the above operation,
The distribution data of the delay time of the test packet data in the system 2 is measured. As described above, when the transmission number of the test packet data is set to 5, the transmission circuit 12 transmits the test packet data generated by the test packet data generation circuit 11 five times (5 Times) and the above operation is repeated.

FIG. 3 shows a specific example of the memory data 16A of the distribution memory 16 thus measured.
In the example of FIG. 3, the delay time of the test packet data is 2 m
It can be seen that the delay time is in the range from s to 10 ms, and the largest delay time is 8 ms. Also, it can be seen that the delay time of the test packet data is usually in the range of 5 ms to 8 ms.

The control circuit 18 reads out each memory data 16A representing the distribution of the delay time stored in the distribution memory 16 and outputs it to an external display device (not shown) or an output device (not shown) such as a printer. Output to The user can recognize the distribution of the delay time of the test packet data in the test target system 2 from the delay time distribution data displayed and output on the display device and the output device.

The reading of each memory data 16A stored in the distribution memory 16 is performed, for example, once a day. After reading the memory data 16A stored in the distribution memory 16 via the control circuit 18, the user may erase (reset) the memory data 16A from the distribution memory 16 via the control circuit 18.

In the above-described embodiment, the transmission interval / number of transmissions of the test packet data by the transmission circuit 12 is set by the transmission interval / number-of-transmissions setting circuit 13, but the present invention is not limited to this. Instead, the generation interval / generation number setting circuit (setting unit) may be configured to set the generation interval of the test packet data by the test packet data generation circuit 11 and the generation number generated at one start.

Although the delay time distribution measuring circuit 10 is provided outside the system 2 in the above embodiment, it may be incorporated inside the system 2. Further, a configuration may be adopted in which a timer is provided in the delay time distribution measuring circuit 10 and when the set time of the timer is reached, the start of the process of measuring the delay time distribution of packet data is automatically started.

In the above embodiment, the addition circuit 17
Is configured to count up (+1) the frequency of the memory data 16A stored at a predetermined address of the distribution memory 16 and write it to the predetermined address of the distribution memory 16, but the present invention is not limited to this. The subtraction circuit counts down the frequency of the memory data 16A by one (-1).
Then, the data may be written to a predetermined address of the distribution memory 16. In this case, the memory data 16A of a certain frequency is stored in each address of the distribution memory 16 in the initial state, and the memory data 16A of the certain frequency is gradually counted down. Further, it may be configured by an arithmetic circuit other than the addition circuit 17 and the subtraction circuit.

In the above embodiment, the transmission circuit 12
Outputs a reset signal to the counter 15 before the start signal is output to the counter 15 to reset the count value. However, the present invention is not limited to this.
May simultaneously output a reset signal and a start signal to the counter 15 so that the counter 15 resets the count value and simultaneously starts counting the delay time.

As described above, according to this embodiment,
The sending circuit 12 sends the test packet data to the system 2 and outputs a start signal to the counter 15 at the same time. The extracting circuit 14 extracts the test packet data passed through the system 2 and outputs a stop signal to the counter 15 at the same time. Accesses the distribution memory 16 using the count value of the delay time counted from the reception of the start signal to the reception of the stop signal as an address,
Since the memory data 16A stored at the address accessed by the distribution memory 16 is output to the adder circuit 17, and the adder circuit 17 counts up the frequency of the memory data 16A by one and writes it to the address. The processing load when finding the distribution of time can be reduced,
The distribution of delay time can be obtained at high speed,
This can be realized only by the hardware configuration, and it is possible to suppress the complexity of the device configuration and increase in cost.

Since the transmission interval / transmission number setting circuit 13 is configured to set the interval at which the transmission circuit 12 transmits test packet data and the number of test packet data transmitted at one start, the test is performed. It is not necessary to start the transmission every time packet data is transmitted, and the distribution of delay time can be measured efficiently.

The control circuit 18 controls the memory data 16A for each delay time stored in the distribution memory 16.
Is read and output to the outside, so that the user can immediately check the distribution of the delay time.

The sending circuit 12 selects packet data and test packet data sent from the data line 1 to the system 2 and sends them to the system. The extracting circuit 14 identifies and extracts the packet data and the test packet data. As a result, the distribution of the delay time of the system 2 currently performing the packet communication can be measured.

Further, since the transmitting circuit 12 transmits the test packet data to the system 2 at a timing at which the test packet data can be transmitted, it does not hinder the packet communication in the system 2 when measuring the distribution of the delay time.

[0048]

As described above, according to the present invention, a test packet data generator for generating test packet data,
The test packet data generated by the test packet data generation unit is transmitted to the system, and a transmission unit that outputs a start signal simultaneously with the transmission of the test packet data, and the test packet data that has passed through the system is extracted. The extraction unit that outputs a stop signal simultaneously with the extraction of data, and starts counting when it receives a start signal output from this transmission unit, stops counting when it receives a stop signal output from the extraction unit, and counts the count. A counter that accesses the count value of the delay time as an address, and frequency data stored in the address accessed from the counter are output, and frequency data in which the frequency data is counted up or down by one is stored in the address. The storage unit and the frequency data output from the storage unit And an arithmetic unit that counts up or down one by one and writes the result to the address of the storage unit, so that the processing load when obtaining the distribution of the delay time can be reduced, and the distribution of the delay time can be obtained at high speed. In addition to this, the present invention can be realized only by the hardware configuration, and has the effect of suppressing the complexity of the device configuration and the increase in cost.

Further, according to the present invention, the setting unit for setting the interval at which the transmitting unit transmits the test packet data and the number of test packet data to be transmitted at one start is also provided. It is not necessary to start the operation every time the operation is performed, and the distribution of the delay time can be measured efficiently.

Further, according to the present invention, the test packet data generating section is provided with the setting section for setting the interval at which the test packet data is generated and the number of test packet data generated at one start. In addition, there is no need to activate the test packet data every time the test packet data is transmitted, and the delay time distribution can be measured efficiently.

Further, according to the present invention, since a control unit for reading out frequency data for each delay time stored in the storage unit and outputting the data to the outside is also provided, the user can immediately confirm the delay time distribution in the system. It has the effect that it can be done.

Further, according to the present invention, the transmitting section selects packet data and test packet data transmitted from the data line to the system and transmits them to the system, and the extracting section identifies the packet data and test packet data. As a result, the distribution of the delay time of the system that is currently performing the packet communication can be measured.

Further, according to the present invention, the transmitting section transmits the test packet data to the system at a timing at which the test packet data can be transmitted. Therefore, when measuring the distribution of the delay time, packet communication in the system is obstructed. The effect that it can prevent is produced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a delay time distribution measuring device according to the present invention.

FIG. 2 is a block diagram showing a count-up operation of memory data in a distribution memory.

FIG. 3 is a diagram showing a specific example of memory data stored in a distribution memory.

[Explanation of symbols]

Reference Signs List 1 data line 2 system 10 delay time distribution measurement circuit (delay time distribution measurement device) 11 test packet data generation circuit (test packet data generation unit) 12 transmission circuit (transmission unit) 13 transmission interval / transmission number setting circuit (setting unit) 14 Extraction Circuit (Extraction Unit) 15 Counter 16 Distribution Memory (Storage Unit) 17 Addition Circuit (Operation Unit) 18 Control Circuit (Control Unit)

Claims (6)

[Claims] 1. A test packet data generating unit for generating test packet data, transmitting the test packet data generated by the test packet data generating unit to a system, and outputting a start signal simultaneously with the transmission of the test packet data A transmitting unit that extracts the test packet data that has passed through the system, and outputs a stop signal simultaneously with the extraction of the test packet data; and a count when receiving the start signal output from the transmitting unit. The counter starts when the stop signal output from the extraction unit is received, and the counter stops accessing the count value of the counted delay time as an address, and the frequency stored in the address accessed from the counter. Outputs data and counts up the frequency data by one Has a storage unit for storing count-down frequency data at the address, and an arithmetic unit for counting up or counting down the frequency data output from the storage unit by one and writing the count data to the address of the storage unit. A delay time distribution measuring device characterized by the above-mentioned. 2. The delay time according to claim 1, further comprising a setting unit that sets an interval at which the transmitting unit transmits the test packet data and a number of the test packet data to be transmitted at one start. Distribution measuring device. 3. The apparatus according to claim 1, further comprising a setting unit for setting an interval at which the test packet data generation unit generates the test packet data and a generation number of the test packet data generated by one start. Delay time distribution measuring device. 4. The control device according to claim 1, further comprising a control unit for reading out frequency data for each delay time stored in the storage unit and outputting the data to the outside. Delay time distribution measuring device. 5. A transmitting section selects packet data and test packet data transmitted from the data line to the system and transmits them to the system, and the extracting section identifies the packet data and the test packet data to identify the packet data and the test packet data. The method according to any one of claims 1 to 4, wherein extraction is performed.
The delay time distribution measuring device according to the item. 6. The delay time distribution measuring apparatus according to claim 5, wherein the transmitting section transmits the test packet data to the system at a timing at which the test packet data can be transmitted.