JPH06139158A - Method for monitoring common bus - Google Patents

Abstract

PURPOSE:To sufficiently extend a data reading period, to shorten an arbitration period and to improve the using efficiency of a common bus by reading out data only at the time of acquiring common bus using right without reading out them during the period of arbitration. CONSTITUTION:Data matched with a trigger condition written in a trigger RAM 1 are extracted from a multiprocessor system common bus 5 and written in a RAM 2. At the time of reading out data, a CPU 3 outputs a common bus using request to an arbitor 4 for outputting a common bus using right request and executing arbitration, and when the using right is obtained, reads out data. Consequently a data reading period matched with a trigger condition can be sufficiently extended, the arbitration period can be shortened independently of data reading and the using efficiency of the common bus can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a common bus monitoring method such as a monitor controller for wireless communication using a multiprocessor system.

In a wireless communication supervisory controller using a multiprocessor system, a monitoring circuit monitors data from a common bus in accordance with a trigger condition consisting of information such as contents of transfer data and timing thereof, and a RAM.
Writing, reading, and normal / abnormal operation of the device are judged, but as a monitoring circuit, the design of the read timing from the RAM is easy and the arbitration time can be shortened to improve the usage efficiency of the common bus. Is required.

[0003]

2. Description of the Related Art FIG. 5 is a block diagram of a conventional monitoring circuit, and FIG. 6 is a time chart of each part of FIG.

In the trigger RAM 1'of FIG. 5, information such as the content of transfer data and its timing, which is a trigger condition necessary for the wireless communication monitoring and control device to judge whether it is normal or abnormal, is written. The data on the common bus 5 which meets the above trigger conditions is (STROB
While the data strobe shown in E) is at the L level, it is input to the clock terminal of the counter 16 via the buffer 20, the trigger RAM 1 ', and the AND circuit 19, the counter 16 is incremented, and the incremented count value is used as an address. , Trace R via buffer 17
Input to AM2 '.

Then, (TRA) of the trace RAM of FIG.
The trace RAM 2 ′ is enabled during the period indicated by (CEEBL), writing during the period indicated by (WE) is enabled, address data is taken in during the period indicated by (address data), and the above data is written into the trace RAM 2 ′.

When reading the data written in the trace RAM 2 ', the CPU 3 issues a common bus use request to the arbiter 4', and the arbiter 4 'issues a common bus use right request to perform arbitration. Of (ABITOR)
During the period shown in (1), the CPU 3 enables the read side of the trace RAM 2 ′ via the bidirectional buffer 21 as shown in (CPUEBL) of the CPU in FIG.
The same address as that written in is output in the period shown in, and the data is read in the period shown in (read data).

In FIG. 6, the data writing period and the data reading period are opposite, but the data reading period is the next arbitration period. That is, the data can be read at any time by issuing a common bus use request to the arbiter 4 '.

Although the arbitration is established and the CPU to which the common bus use right is given uses the common bus, the other CPUs
During that time, the common bus cannot be used.

[0009]

However, if the arbitration period is shortened in order to increase the common bus use efficiency, the CP
There is a problem that the period in which U reads data from the trace RAM becomes short, which makes it difficult to design the read timing.

It is an object of the present invention to provide a common bus monitoring method capable of providing a sufficient data read period, shortening the arbitration period, and improving the common bus use efficiency.

[0011]

FIG. 1 is a block diagram showing the principle of the present invention. As shown in FIG. 1, from the common bus 5 of the multiprocessor system, data matching the trigger condition written in the trigger RAM 1 is written in the RAM 2, and the CPU
The CPU 3 issues a common bus use request to the arbiter 4 which issues a common bus use right request and arbitrates when the use right is given, and when the use right is given, the CPU 3 reads it.

[0012]

According to the present invention, the data on the common bus 5 which meets the trigger condition is written in the RAM 2.

When the CPU 3 reads this, a common bus use request is issued to the arbiter 4, a common bus use right request is issued from the arbiter 4 to arbitrate, and when the use right is obtained, RA
Read the data written in M2.

That is, since the data is not read during the arbitration period, the arbitration period can be shortened regardless of the data read to improve the common bus use efficiency, and the data read has acquired the right to use the common bus. Since the data is read from time to time, a sufficient data read period can be secured.

[0015]

2 is a block diagram of a monitoring circuit of an embodiment of the present invention, FIG. 3 is a block diagram of a monitoring circuit of another embodiment of the present invention, and FIG. 4 is a monitoring circuit of another embodiment of the present invention. It is a block diagram.

In the trigger RAM 1 of FIG. 2, information such as the contents of transfer data and the timing thereof, which are trigger conditions necessary for the wireless communication monitoring and control device to judge whether the monitoring control device is normal or abnormal, is written. When the data on the common bus 5 meets the trigger condition written in the trigger RAM 1, the trigger RAM 1 outputs L level, the output of the OR circuit 8 is set to L level, the trace RAM 2 is write enabled, and both Data matching the trigger condition input from the buffer 6 is input and written in the trace RAM 2.

When reading, the CPU 3 issues a common bus use request to the arbiter 4 and a common bus use right request from the arbiter 4 to cause arbitration. When the arbiter 4 obtains the usage right, the arbiter 4 outputs the H level from the WIN terminal,
The write enable side of the bidirectional buffer 6 and the trace RAM 2 is disabled, and it is inverted by the knot circuit 9 to the L level, the out enable side of the trace RAM 2 is enabled, and the bidirectional buffer 7 is also enabled. While acquiring, the writing to the trace RAM 2 from the common bus 5 is disabled and the CPU 3
From the trace RAM 2 via the bidirectional buffer 7 during the (STROBE) L level period of the common bus of FIG.
Read the data.

3 and 4 show that the common bus use request is issued to the arbiter 4 of FIG. 2 when the common bus 5 is as free as possible, which is different from FIG. 2 in FIG. 4 is that the AND circuit 11, the buffer 12 and the counter 13 are provided. The difference from FIG. 2 in FIG. 4 is that the AND circuits 11 and 14 and the one-sailboat multi 15 are provided. This will be described below.

In FIG. 3, an address strobe GAS indicating that an address is being fetched at the L level on the common bus 5 is
When the H level is input to the clear terminal of the counter 13 via the buffer 12 and the address is not being taken in for a certain period of time, the H level is output from the carry-out output of the counter 13 and is input to the AND circuit 11. While the H level is being input, the common bus use request from the CPU 3 is output and input to the arbiter 4.

In FIG. 4, the address strobe GAS indicating that the address is being taken in at the L level and the data strobe GDS indicating that the data is being taken in at the L level in the common bus 5 are input to the AND circuit 14, and the address and the data are input. If both are at the H level but not being taken in, the H
The level is output and input to the AND circuit 11, and while the output of the one sailboat multi 15 is at the H level, the AND circuit 1 is output.
1 to output a common bus use request from the CPU 3,
I am trying to input to arbiter 4.

[0021]

As described in detail above, according to the present invention, a sufficient period for reading data that meets the trigger condition can be obtained.
Moreover, there is an effect that the arbitration period can be shortened regardless of the data reading, and the common bus usage efficiency can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of the present invention,

FIG. 2 is a block diagram of a monitoring circuit according to an embodiment of the present invention,

FIG. 3 is a block diagram of a monitoring circuit according to another embodiment of the present invention,

FIG. 4 is a block diagram of a monitoring circuit according to another embodiment of the present invention,

FIG. 5 is a block diagram of a conventional monitoring circuit,

FIG. 6 is a time chart of each part of FIG.

[Explanation of symbols]

 1, 1'is a trigger RAM, 2 is a RAM, trace RAM, 2'is a trace RAM, 3 is a CPU, 4, 4'is an arbiter, 5 is a common bus, 6, 7 and 21 are bidirectional buffers, 8 is an OR A circuit, 9 is a knot circuit, 11, 14 and 19 are AND circuits, 12, 17, 18, and 20 are buffers, 13 and 16 are counters, and 15 is a one-sided sailboat multi.

Claims (1)

[Claims] 1. A multiprocessor type common bus (5)
Data that meets the trigger condition written in the trigger RAM (1) is written in the RAM (2)
When (3) reads, the CPU (3) issues a common bus use request to the arbiter (4) which issues a common bus use right request and performs arbitration, and when the use right is given, the CPU (3) reads it. Characteristic common bus monitoring method.