JP2006092077A - Bus system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a bus system allowing a bus master to know completion of writing though using a memory controller not having a function notifying the bus master about the completion of the writing of data into a memory. <P>SOLUTION: This bus system 1 comprises: a plurality of buses 11a, 11b; bridges 12a, 12b connecting the buses 11a, 11b; the memory 13 storing the data; the memory controller 14 directly accessing the memory 13; the bus master 15 requiring the writing or reading of the data; and a writing completion notifying device 16. The writing completion notifying device 16 transmits the writing requirement from the bus master 15 to the memory controller 14, issues the reading requirement with a writing address designated by the writing requirement as a reading address, and imparts writing completion notification to the bus master at the time point when receiving reading completion notification from the memory controller 14. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a bus system in which a plurality of buses are connected by a bridge, and more particularly to a bus system in which a bus master can reliably recognize completion of writing to a memory.

  A bus system in which a device that performs predetermined processing and a device that requests processing is connected by a bus is widely used in various devices including computers. A device that requests processing is called a bus master, and a device that performs processing is called a bus slave. The bus master includes, for example, a CPU (Central Processing Unit) and a DMAC (Direct Memory Access Controller). When the bus master requests writing to the memory or reading from the memory, the CPU immediately takes a bus if the bus is free. If it is not available, arbitration is performed and the use of the bus is permitted. When the use is permitted, the memory controller, which is a bus slave, directly accesses the memory and writes and reads data.

  In general, when there is a request from the bus master, the memory controller notifies the bus master that the request has been accepted via the bus, but does not necessarily notify that the requested processing has been completed. In other words, in response to a read request from the memory, the memory controller notifies the bus master of the completion of reading via the bus when the reading of data from the memory is completed, but in response to a write request to the memory. Thus, even if the memory controller writes data to the memory, it does not notify the bus master of the writing completion. For this reason, the bus master that has requested writing to the memory cannot know when the writing to the memory has been completed.

  In recent years, for the purpose of eliminating bus congestion, etc., priorities have been given to requests, and arbitration based on the priorities has been performed. After the bus master issues a request, processing according to that request The time until is executed is likely to fluctuate. For this reason, the order of writing data to the memory and reading data from the memory may be reversed, and a situation may occur in which correct data cannot be read.

  For example, if the bus master requests the CPU to write data to the memory after requesting the data to be written to the memory, and the CPU requests to read the data, the data is written before the data writing to the memory is completed. May be read out and old data may be read out. Normally, write and read requests to the same address from the same bus master are processed in the order of request, so if the bus master requests the data read after the bus master requests the data write, it is correct. Data is read out.

As a conventional technique for solving the above-described problem, an interrupt delay device that delays an interrupt signal to a CPU for a predetermined time has been proposed (see, for example, Patent Document 1).
Japanese Patent Laid-Open No. 9-274571

In addition, as another conventional technique for solving the above-described problem, a first input / output control unit that notifies that a write request is being held, and an interrupt signal to the CPU is suspended while receiving the notification, There has also been proposed an information processing apparatus including a second input / output control unit that issues an interrupt signal that has been suspended when writing is completed (see, for example, Patent Document 2).
Japanese Patent Laid-Open No. 9-16541

There is also a bus system in which a plurality of buses having different characteristics such as speed are connected by a bridge (see, for example, Patent Document 3). Particularly in such a bus system, the time from when a write request is made until when data is actually written to the memory is likely to vary, and the order of writing data to the memory and reading data from the memory is reversed. There is a tendency that correct data cannot be read.
JP-A-9-237223

  Certainly, if the above-described conventional technology is adopted, even in an information processing system having a large number of buses and bus masters, old data is read by reading data before data writing to the memory is completed. Can be avoided.

  However, in the technique of Patent Document 1, since the interrupt signal to the CPU is always delayed for a certain time regardless of the bus usage rate or the like, when writing is completed in a short time such as when the bus usage rate is low. The opening of the bus is unnecessarily delayed, which is a factor that hinders the speed of memory access. In addition, this problem further hinders the speed of memory access because a delay time needs to be set long in a bus system in which a plurality of buses having different characteristics such as speed are connected by a bridge.

  Further, in the technique of Patent Document 2, it is necessary to newly define DMA write and interrupt processing, which not only increases the data width but also requires a great deal of effort to expand the existing bus system. There is.

  The above problem can be solved by adopting a configuration that notifies the bus master of the completion of writing when the memory controller completes the writing of data to the memory. However, a manufacturer of a device that employs a bus system does not necessarily manufacture a bus, but rather a proprietary bus manufactured by another person such as SoC (System-on-Chip) (for example, PLB (IBM) ), AMBA (ARM), PCI (industry standard), etc.), and a bus system is often constructed by connecting a plurality of buses with a bridge. In such a case, it is extremely difficult because it takes a lot of cost and time to review the configuration of the bus itself from the beginning, and it is practically impossible to give the bus the function of notifying the bus master of the completion of writing.

  The present invention has been made in view of such problems, and even in a bus system in which a plurality of buses are connected by a bridge, without hindering an improvement in the speed of memory access, and without changing the configuration of the bus itself. An object of the present invention is to provide a bus system in which a bus master can know that writing to a memory has been completed.

  In order to achieve the above object, according to the present invention, a plurality of buses connected by a bridge, a memory for storing data, a bus connected to the memory, and data to the memory in response to a request given through the bus In a bus system comprising a memory controller that writes data and reads data from the memory, and a bus master that requests the memory controller to write data to the memory and read data from the memory via the bus, the bus and the bus master Connected, transmits a write request from the bus master to the memory controller, then requests the memory controller to read data from the memory by specifying the same address as that specified in the write request, When the memory controller reads data from the memory, Comprising a write completion notification means for notifying that the writing of data to the Li is complete to the bus master.

  In response to a read request, the memory controller notifies the request source via the bus that the read has been completed when the read from the memory is completed. Can know. In addition, the address of the memory that the write completion notification means requests to read is the same as the address of the write request from the bus master, and access requests to the same address from the same bus master are processed in the order of request, so the write is completed. When the notification means knows the completion of reading, the writing corresponding to the writing request from the bus master is completed. Therefore, the bus master can surely know that the requested write has been completed by the notification from the write completion notification means.

  Here, only when the notification is requested from the bus master, the write completion notification means requests the memory controller to read data from the memory and notifies the bus master that the data writing to the memory is completed. It is good to. In this way, when the bus master does not need to know the completion of writing, useless reading can be omitted, and the efficiency of the entire system is improved.

  According to the bus system of the present invention, even when the memory controller does not have a function of notifying the bus master of completion of data writing to the memory, the bus master can surely know that the requested writing has been completed. It is possible to prevent a situation in which the reading order is reversed and correct data cannot be read.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The configuration of the bus system 1 of the present embodiment is schematically shown in FIG. The bus system 1 includes a plurality of buses 11a and 11b, bridges 12a and 12b connecting the buses 11a and 11b, a memory 13, a memory controller 14, a bus master 15, and a write completion notifier 16. Although only two buses 11a and 11b are shown in FIG. 1, there may be three or more buses. In that case, add a bridge and connect all the buses directly or indirectly.

  The memory controller 14 is connected to one bus 11 b and the memory 13, and writes data to the memory 13 and reads data from the memory 13 in response to a request given via the bus 11 b. The data to be written to the memory 13 and the address of the memory 13 to which the data is to be written are given via the bus 11b together with the write request, and the address of the memory 13 from which the data is to be read is also given via the bus 11b together with the read request. The read data is transmitted via the bus 11b.

  The bus master 15 requests the memory controller 14 to write data to the memory 13 and read data from the memory 13 via the bus 11a, the bridges 12a and 12b, and the bus 11b. When the memory controller 14 receives a write request or a read request from the bus master 15, the memory controller 14 notifies the bus master 15 that the request has been received, and when the data is read from the memory 13 in response to the read request from the bus master 15, the memory controller 14 Is notified to the bus master 15. However, the bus master 15 is not directly connected to the bus 11a.

  The write completion notifier 16 is connected to the bus 11a and the bus master 15, and transmits a write request and a read request from the bus master 15 to the bus 11a, and also notifies from the bus 11a and a read request from the bus master 15. Accordingly, the data read from the memory 13 by the memory controller 14 is transmitted to the bus master 15.

  As described above, the memory controller 14 notifies the completion of reading when data is read from the memory 13, but notifies the completion of writing when data is written to the memory 13 in response to a write request from the bus master 15. Absent.

  However, in the bus system 1, when the write completion notifier 16 interposed between the bus master 15 and the bus 11a transmits the write request from the bus master 15 to the bus 11a, the address specified by the write request is subsequently issued. Request to read data from. When the read completion notification is received from the memory controller 14, the bus master 15 is notified that the writing has been completed.

  The memory controller 14 recognizes the read request from the write completion notifier 16 as a read request from the bus master 15 and processes access requests to the same address from the same bus master in the order of request. For this reason, when the write completion notification device 16 receives a read completion notification from the memory controller 14, the write processing corresponding to the write request from the bus master 15 transmitted by the write completion notification device 16 is completed. Therefore, the bus master 15 can know without error that the writing corresponding to its own writing request has been completed by the writing completion notification from the writing completion notifier 16.

  In relation to the write request from the bus master 15, signals and information transmitted between the bus master 15, the write completion notifier 16, and the memory controller 14 are shown in FIG. The signal and information transmitted from the bus master 15 to the write completion notifier 16 include a write address MAddr that is an address of the memory 13 to which data is to be written, write data MWriteData that is data to be written to the memory 13, and data of the data to the memory 13. There are a write request signal MWWriteReq for requesting writing, and a notification request signal MAckReq for requesting the write completion notifier 16 for notification of write completion.

  In a signal and information transmitted from the write completion notifier 16 to the memory controller 14 via the bus 11a, the bridges 12a and 12b, and the bus 11b, a write address Addr that is an address of the memory 13 to which data is written is written in the memory 13. There are write data WriteData that is data to be written, a write request signal WriteReq that requests writing of data to the memory 13, and a read request signal ReadReq that requests reading of data from the memory 13.

  Note that the write address MAddr, the write data MWriteData, and the write request signal MWriteReq transmitted from the bus master 15 to the write completion notifier 16, the write address Addr, the write data WriteData transmitted from the write completion notifier 16 to the memory controller 14, The contents of the write request signal WriteReq are the same.

  The write completion notifier 16 may be configured to transfer the write address MAddr from the bus master 15 to the memory controller 14 as it is as the write address Addr, or to detect the write address MAddr from the bus master 15 and write the same contents. The address Addr may be generated and transmitted to the memory controller 14. The same applies to the write data MWWriteData, WriteData, and the write request signals MWWriteReq, WriteReq.

  A signal and information transmitted from the memory controller 14 to the write completion notifier 16 via the bus 11b, the bridges 12b and 12a, and the bus 11a include an acceptance notification signal BusAck for notifying that a write request and a read request have been accepted, and the memory 13 There are read data ReadData that is data read from and a read completion notification signal ReadAck that informs that reading of data from the memory 13 is completed.

  The signal and information transmitted from the write completion notifier 16 to the bus master 15 include an acceptance notification signal MBusAck notifying that the write request has been accepted by the memory controller 14 and the completion of data writing to the memory 13. There is a write completion notification signal MWWriteAck to notify. The reception notification signal MBusAck is transmitted when the reception notification signal BusAck is received from the memory controller 14, and the write completion notification signal MWWriteAck is transmitted when the read completion notification signal ReadAck is received from the memory controller 14.

  The write completion notifier 16 transmits the read request signal ReadReq to the memory controller 14 only when it receives the notification request signal MAckReq together with the write request signal MWWriteReq from the bus master 15. Therefore, if there is no notification request signal MAckReq from the bus master 15, there is no read completion notification signal ReadAck from the memory controller 14, and the write completion notification device 16 does not transmit the write completion notification signal MWWriteAck to the bus master 15. Thus, when the bus master 15 does not need to know the completion of writing, it is possible to avoid the waste of performing a reading process and a notification of the completion of writing.

  The time chart of FIG. 3 shows the transmission and reception timings of the above signals and information when the bus master 15 requests writing to the memory 13 without requesting writing completion notification (without transmitting the notification request signal MAckReq). Shown in

  First, the bus master 15 turns on the write request signal MWWriteReq (value 1), and simultaneously sets the write address MAddr and the write data MWWriteData. In response to this, the write completion notifier 16 turns on the write request signal WriteReq and sets the write address Addr and the write data WriteData.

  Upon receiving the write request signal WriteReq, the memory controller 14 turns on the reception notification signal BusAck, and in response to this, the write completion notification device 16 turns on the reception notification signal MBusAck. The bus master 15 that has received the acceptance notification signal MBusAck returns the write request signal MWWriteReq to off (value 0). The memory controller 14 writes data into the memory 13 after turning on the reception notification signal BusAck (not shown).

  The time chart of FIG. 4 shows the timing of transmission and reception of the above signals and information when the bus master 15 requests writing to the memory 13 while requesting writing completion notification (transmitting the notification request signal MAckReq). .

  First, the bus master 15 turns on the write request signal MWWriteReq and the notification request signal MAckReq, and simultaneously sets the write address MAddr and the write data MWWriteData. In response to this, the write completion notifier 16 turns on the write request signal WriteReq and sets the write address Addr and the write data WriteData.

  Upon receiving the write request signal WriteReq, the memory controller 14 turns on the reception notification signal BusAck, and in response to this, the write completion notification device 16 turns on the reception notification signal MBusAck. The bus master 15 that has received the acceptance notification signal MBusAck turns off the write request signal MWWriteReq and the notification request signal MAckReq. The memory controller 14 writes data into the memory 13 after turning on the reception notification signal BusAck (not shown).

  The write completion notifier 16 that has received the notification request signal MAckReq together with the write request signal MWWriteReq keeps the write address Addr as it is after receiving the reception notification signal BusAck and turns on the reception notification signal MBusAck, and further reads the read request signal ReadReq. Turn on. The memory controller 14 that has received the read request signal ReadReq turns on the reception notification signal BusAck, and the write completion notifier 16 that has received this turns off the read request signal ReadReq. The write completion notifier 16 does not turn on the reception notification signal MBusAck when receiving the reception notification signal BusAck for the read request signal ReadReq.

  In the bus system 1, the same signal line is also used for the write address and the read address (address of the memory 13 from which data is read), and the write address Addr given to the memory controller 14 together with the read request signal ReadReq is recognized as the read address. The The memory controller 14 turns on the acceptance notification signal BusAck in response to the read request signal ReadReq, reads data from the memory 13 (not shown), and turns on the read completion notification signal ReadAck when the read is completed. To.

  Upon receiving the read completion notification signal ReadAck, the write completion notification device 16 turns on the write completion notification signal MWWriteAck, whereby the bus master 15 confirms that the memory controller 14 has written the data into the memory 13 in response to the write request signal MWWriteReq. know. Note that the read data ReadData is given from the memory controller 14 to the write completion notifier 16, but the write completion notifier 16 only turns on the write completion notification signal MWWriteAck to notify the bus master 16 of the read completion, and the read data ReadData. Is discarded without giving to the bus master 16.

  In the bus system 1, the same signal line is used for both the write address and the read address. However, the write address and the read address may be transmitted by different signal lines. In that case, the write completion notifier 16 may set the write address MAddr from the bus master 15 as a read address.

  Here, only one bus master 15 and one write completion notifier 16 are shown, but the number of bus masters 15 is not limited, and a write completion notifier 16 is provided for each bus master 15 that requests writing to the memory 13. It is good to do so.

The block diagram which shows typically the structure of the bus system of one Embodiment of this invention. The figure which shows the signal and information which are transmitted / received in relation to the write request from a bus master in the said bus system. 4 is a time chart showing signal and information transmission / reception times when the bus master requests writing without requesting writing completion notification in the bus system. 4 is a time chart showing signal and information transmission / reception times when the bus master requests writing while requesting writing completion notification in the bus system.

Explanation of symbols

1 Bus System 11a, 11b Bus 12a, 12b Bridge 13 Memory 14 Memory Controller 15 Bus Master 16 Write Completion Notifier MAAddr, Addr Write Address MWWriteData, WriteData Write Data MWriteReq, WriteReq Write Request Signal MBusAck Signal Request Read request signal ReadData Read data ReadAck Read completion notification signal MWriteAck Write completion notification signal

Claims (2)

A plurality of buses connected by a bridge, a memory for storing data, and a memory connected to the bus and the memory for writing data to the memory and reading data from the memory in response to a request given through the bus In a bus system comprising a controller and a bus master requesting the memory controller to write data to the memory and read data from the memory via the bus,
Connected to the bus and the bus master, transmits a write request from the bus master to the memory controller, and then specifies the same address as that specified in the write request to read the data from the memory to the memory controller And a write completion notifying means for notifying the bus master that the writing of data to the memory is complete when the memory controller reads the data from the memory.   The write completion notifying means requests the memory controller to read data from the memory only when a notification is requested from the bus master, and notifies the bus master that the data writing to the memory is completed. The bus system according to claim 1.

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