JP2005228188A - Information processing system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information processing system capable of stably performing a memory access at high speed without requiring a configuration change in an existing bus. <P>SOLUTION: This information processing system 1 comprises a monitoring device 15 monitoring transactions from bus masters 11a-11d to detect the progress of access processing to a memory 12, and transmitting an instruction signal according to the detection result to any one of the bus masters 11a-11d via signal lines 15a-15d except internal buses A and B. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an information processing system that performs memory access via a bus.

  Conventionally, a bus that is a signal transmission path, a plurality of bus masters (for example, a CPU [Central Processing Unit] or a DMAC [Direct Memory Access Controller]) that transmits and receives signals through the bus, and an information signal are stored. And a memory controller that controls reading and writing of information signals to and from the memory in response to a processing request (write transaction or read transaction) input from the bus master via the bus. In general, the bus master generates an interrupt signal to the CPU when access to the memory is completed (for example, when transmission of a write transaction is completed), and notifies the completion of its memory access processing.

  However, in an information processing system that has a large number of buses and bus masters, the time between when a write transaction is sent and when the actual write processing to the memory is executed due to the bus congestion and arbitration order. In addition, there is a considerable time lag. For this reason, a so-called “overtake of interrupt signal” occurs, and the CPU that received the interrupt signal from the bus master (or another bus master separately activated by the CPU) may not be able to read the correct information signal from the memory. .

  As a conventional technique for solving the above-described problem, an interrupt delay device that delays an interrupt signal to a CPU for a predetermined time is disclosed and proposed (for example, see Patent Document 1).

As another conventional technique for solving the above-mentioned problem, a first input / output control unit for notifying that a write transaction is being held and an interrupt signal to the CPU are suspended while receiving the notification. A second input / output control unit that issues an interrupt signal that has been suspended when the write operation is completed, and an information processing apparatus that includes the second input / output control unit are also disclosed and proposed (see, for example, Patent Document 2). .
Japanese Patent Laid-Open No. 9-274571 Japanese Patent Laid-Open No. 9-16541 JP 2001-14849 A

  Certainly, by adopting the above-described conventional technology, even in an information processing system having a large number of buses and bus masters, it is possible to avoid “passing an interrupt signal”, so that stable memory access can be performed. Become.

  However, in the technique described in Patent Document 1, the CPU is always set for a certain time (maximum delay time from when the write transaction is sent to when the write process to the memory is actually executed) regardless of the bus usage rate or the like. When the write operation is completed in a short period of time, such as when the bus usage rate is low, the bus release is unnecessarily delayed, which hinders the increase in memory access speed. It was.

  In the technique described in Patent Document 2, it is necessary to newly define a DMA write or an interrupt transaction, which not only increases the data width, but also requires a lot of effort to expand the existing bus system. There was a problem.

  As a technique for solving the above-described problem, a configuration in which the bus itself has a function of notifying the completion of write processing to the CPU can be considered. In addition to the cost and time required, there is a problem that it cannot be applied to a system that uses an existing bus that does not have a write processing synchronization function as an asset.

  In any conventional configuration, the bus arbitration process is performed through the CPU. Therefore, when another bus master is started after the transaction of a certain bus master is completed, a time loss is caused by the intervention of the CPU. As a result, it has been a factor that hinders the speed of memory access.

  In view of the above problems, an object of the present invention is to provide an information processing system capable of performing memory access at high speed and stably without requiring a configuration change of an existing bus.

  In order to achieve the above object, an information processing system according to the present invention includes a bus that is a signal transmission path, a plurality of bus masters that exchange signals via the bus, a memory that stores information signals, A memory controller that controls reading and writing of the information signal to and from the memory in response to a processing request input from the bus master via the bus, and monitors a transaction from the bus master to the memory A monitoring apparatus is provided that detects the progress of access processing and sends a command signal corresponding to the detection result to one of the bus masters via a signal line other than the bus.

  In the information processing system configured as described above, after the bus master has finished sending the write transaction for requesting the writing of the information signal to the memory, the bus master continuously sends an event transaction indicating the sending completion, The monitoring circuit may be configured to detect a progress status of access processing to the memory based on whether or not the input transaction is the event transaction.

  In the information processing system having the above-described configuration, each of the write transaction and the event transaction includes a mask attribute for setting a valid byte lane for the data width of the memory, and the bus master When generating a transaction, the mask attribute is set so that all byte lanes are masked, and the monitoring device determines whether or not the input transaction is the event transaction when detecting the progress of the access process to the memory. It is preferable to make a determination based on the mask attribute.

  In the information processing system having the above-described configuration, each of the write transaction and the event transaction includes attribute information other than the mask attribute, and the bus master generates an arbitrary response to the monitoring device when generating the event transaction. The monitoring device may be configured to send the command signal to one of the bus masters based on the instruction written in the attribute information of the input event transaction.

  In the information processing system configured as described above, the bus master writes, in the attribute information, a value in which a command for requesting notification of completion of its own ID and its transaction is written to the attribute information when generating the event transaction. The monitoring device waits for generation of an interrupt signal for another bus master until receiving the transaction completion notification from the controller, and the monitoring device sends the transaction completion notification based on the ID and command written in the input event transaction attribute information. It may be configured to send to the bus master.

  In the information processing system configured as described above, the bus master writes, in the attribute information, a value in which a command requesting another bus master's ID and its activation signal is set when generating the event transaction, May be configured to send the activation signal to the other bus master based on the ID and command written in the attribute information of the input event transaction.

  As described above, with the information processing system according to the present invention, it is possible to perform memory access at high speed and stably without requiring a configuration change of an existing bus.

  FIG. 1 is a block diagram showing an embodiment of an information processing system according to the present invention. As shown in the figure, the information processing system 1 (SoC [System On a Chip], ASIC [Application Specific Integrated Circuit], etc.) of the present embodiment has internal buses A and B (internal bus A) that are signal transmission paths. Is a high-speed bus, the internal bus B is a low-speed bus), and a plurality of bus masters (CPU 10 and bus masters 11a and 11b connected to the internal bus A and the internal bus B) that send and receive signals through the internal buses A and B. From the connected bus masters 11c and 11d), the memory 12 for storing information signals (DRAM [Dynamic Random Access Memory], SDRAM [Synchronous DRAM], SRAM [Static RAM], etc.), CPU 10 and bus masters 11a to 11d A memory controller 13 that controls reading and writing of information signals to and from the memory 12 in response to processing requests input via the internal buses A and B; The progress of access processing for the memory 12 is detected with reference to the bridge 14 that connects the buses A and B and the interface of the memory controller 13, and command signals corresponding to the detection result are sent via the signal lines 15a to 15d to the bus master. And a monitoring device 15 for sending to 11a to 11d.

  In the information processing system 1 configured as described above, the CPU 10 is one of a plurality of bus masters.

  On the other hand, as shown in FIG. 2, the bus masters 11a to 11d other than the CPU 10 generate a write transaction for generating a write transaction for requesting an information signal write process to the memory 12, and the transmission completion of the write transaction. An event transaction generation circuit 112 for generating an event transaction to be generated, and after the final write transaction is sent, an interrupt signal to the CPU 10 is not generated immediately, but the event transaction is generated and the memory controller is generated. 13 (substantially the monitoring circuit 15). In FIG. 2, only the internal configuration of the bus master 11a is shown, but the other bus masters 11b to 11d have the same internal configuration.

  The above event transaction will be described in detail. The event transaction generated by the bus masters 11a to 11d has the same data structure as that of the write transaction and the read transaction, and includes attribute information necessary at the minimum for accessing the internal buses A and B. Specifically, as shown in FIG. 3, an address attribute indicating the address information of the memory 12 to be accessed, a data attribute indicating an information signal to be written to the address, and a byte lane effective for the data width of the memory 12 are set. It includes various attribute information such as a mask attribute for setting and a read / write attribute indicating which of the read / write the transaction is instructed.

  Here, the mask attribute is attribute information required when restricting read / write processing of an information signal in the information processing system 1 of the present embodiment using DRAM, SDRAM, SRAM, or the like as the memory 12. The DQM signal corresponds to this as the pin name of the device (for details, see Patent Document 3). For example, when the data width of the memory 12 is 16 bits, but the minimum unit of the access width requested by the information processing system 1 is 8 bits (1 byte), it is not necessary to use the mask attribute. Masking byte lanes prevents erroneous data from being read / written.

  In other words, in the mask attribute of the write transaction and the read transaction generated by the bus masters 11a to 11d, one of the byte lanes must be valid to read / write the information signal to / from the memory 12, It is unlikely that all byte lanes are masked.

  The information processing system 1 according to the present embodiment is made by paying attention to the above points. Each bus master 11a to 11d sets a mask attribute so as to mask all byte lanes when generating an event transaction. It is supposed to be configured. On the other hand, the monitoring device 15 recognizes the transaction as an event transaction when it detects that the mask attribute of the input transaction masks all the byte lanes when detecting the progress of the memory access process. The memory access process of the bus master that has sent the event transaction is determined to have been completed.

  In this way, by using an existing mask attribute and flagging whether or not it is an event transaction according to the attribute value, the event transaction can be performed without unnecessarily increasing the transaction attribute information. Can be established.

  In the event transaction described above, since there is no byte lane that is enabled by the mask attribute, it is possible to avoid erroneous input / output to the memory 12 by the event transaction.

  Further, since the data attribute can be set to an arbitrary value in the event transaction described above, an arbitrary command for the monitoring device 15 is set by diverting the data attribute, and the monitoring device 15 after the event transaction is detected. It is also possible to control the behavior. This will be described in detail later with a specific example.

  Note that, as described above, the monitoring device 15 of the present embodiment has a simple configuration that simply refers to the interface of the memory controller 13, and therefore can be easily attached to an existing information processing system.

  Hereinafter, the memory access operation of the information processing system 1 configured as described above will be described in detail with a specific example.

  First, as a first operation example, consider a case where a plurality of write transactions are generated from the bus master 11d to the memory 12, and an interrupt signal to the CPU 10 is generated after the write processing is completed.

  In this case, the bus master 11d does not generate an interrupt signal to the CPU 10 immediately after sending the final write transaction, but generates the event transaction and sends it to the memory controller 13. At this time, the bus master 11d writes a value obtained by setting a command requesting its own ID and its transaction completion notification to the data attribute of the event transaction.

  On the other hand, when the monitoring device 15 that references the interface of the memory controller 13 detects that the mask attribute of the input transaction masks all the byte lanes, the monitoring device 15 recognizes the transaction as an event transaction, It is determined that the memory access process of the bus master 11d has been completed. Then, the monitoring device 15 sends a write transaction completion notification (in other words, an interrupt permission notification to the CPU 10) to the bus master 11d via the signal line 15d in accordance with the ID and command written in the data attribute of the event transaction. .

  Receiving the notification, the bus master 11d recognizes that the write transaction to the memory 12 has been completed, and generates an interrupt signal to the CPU 10.

  As described above, in the information processing system 1 of the present embodiment, the waiting time from when the bus master 11d sends the final write transaction to when the interrupt signal to the CPU 10 is generated can be minimized. Even when the write operation is completed in a short time, such as when the bus usage rate is low, the bus can be quickly released. Therefore, memory access can be performed at high speed and stably without requiring a configuration change of the existing bus.

  Next, as a second operation example, consider a case where the bus master 11b is activated and a predetermined process is realized after the write processing to the memory 12 by the bus master 11d is completed.

  Also in this case, the bus master 11d does not generate an interrupt signal to the CPU 10 after sending the final write transaction, but generates the event transaction and sends it to the memory controller 13. At this time, the bus master 11d writes a value obtained by setting the ID of the bus master 11b to be activated next and a command requesting the activation signal into the data attribute of the event transaction.

  On the other hand, when the monitoring device 15 that references the interface of the memory controller 13 detects that the mask attribute of the input transaction masks all the byte lanes, the monitoring device 15 recognizes the transaction as an event transaction, It is determined that the memory access process of the bus master 11d has been completed. Then, the monitoring device 15 sends an activation signal to the bus master 11b via the signal line 15b in accordance with the ID and command written in the data attribute of the event transaction.

  The bus master 11b that has received the activation signal is activated without intervention of the CPU 10 and starts predetermined processing.

  As described above, the information processing system 1 according to the present embodiment can reduce the time loss caused by the CPU, thereby improving the memory access speed. .

  In the above embodiment, the configuration in which the monitoring device 15 is provided immediately before the memory controller 13 to refer to the interface of the memory controller 13 has been described as an example. However, the configuration of the present invention is not limited thereto. It is not a position that can monitor transactions from the bus masters 11a to 11d, and any transaction that reaches the monitoring device 15 can reach the memory controller 13 prior to other transactions. May be provided.

  Further, in the above embodiment, the description has been given by taking as an example a configuration in which an existing mask attribute is diverted and flagging whether or not it is an event transaction according to the attribute value, but the configuration of the present invention Is not limited to this, and when there is no command for masking all the byte lanes on the bus, the number of states of the access attribute for the bus is increased by 1 and flag data for 1 bit is added separately. It does not matter as a configuration. When this configuration is adopted, it is necessary to provide an event transaction discard function in the memory controller in order to avoid erroneous input / output to the memory due to event transactions.

  In the above embodiment, the event transaction generation function is given as an example to the bus masters 11a to 11d. However, the configuration of the present invention is not limited to this, and the function is not limited to this. The internal buses A and B may have a configuration.

  Further, in the above embodiment, the case where the present invention is applied to an SoC or ASIC including each component such as a bus or a bus master has been described as an example. The present invention is not limited, and can be widely applied to the entire information processing system regardless of whether each component is built in or externally attached.

  The present invention is a useful technique for improving the high speed and stability of an information processing system that performs memory access via a bus.

These are block diagrams which show one Embodiment of the information processing system which concerns on this invention. These are block diagrams which show the internal structural example of the bus master 11a. These are figures which show an example of the attribute information contained in the transaction (write / read / event) produced | generated by the bus masters 11a-11d.

Explanation of symbols

1 Information processing system 10 Bus master (CPU)
11a to 11d Bus master (other than CPU)
111 Write transaction generation circuit 112 Event transaction generation circuit 12 Memory (DRAM, SDRAM, SRAM, etc.)
13 Memory Controller 14 Bridge 15 Monitoring Device 15a to 15d Signal Line A High Speed Bus B Low Speed Bus

Claims (6)

A bus serving as a signal transmission path, a plurality of bus masters for transmitting and receiving signals through the bus, a memory for storing information signals, and the processing request input from the bus master via the bus In an information processing system having a memory controller that controls reading and writing of the information signal to and from the memory,
A monitoring device that monitors a transaction from the bus master to detect a progress status of access processing to the memory and sends a command signal corresponding to the detection result to one of the bus masters via a signal line other than the bus; An information processing system characterized by that.   The bus master, after finishing sending the write transaction for requesting the writing process of the information signal to the memory, continuously sends the event transaction indicating the sending completion, and the monitoring circuit The information processing system according to claim 1, wherein the progress of access processing for the memory is detected based on whether or not the transaction is an event transaction.   Each of the write transaction and the event transaction includes a mask attribute for setting a valid byte lane for the data width of the memory, and the bus master masks all the byte lanes when generating the event transaction. The monitoring device sets the mask attribute so as to determine whether or not the input transaction is the event transaction based on the mask attribute when detecting the progress of the access process to the memory. The information processing system according to claim 2.   Each of the write transaction and the event transaction includes attribute information other than the mask attribute, and the bus master writes an arbitrary instruction to the monitoring device in the attribute information when the event transaction is generated, and the monitoring 4. The information processing system according to claim 3, wherein the apparatus transmits the command signal to one of the bus masters based on an instruction written in the attribute information of the input event transaction.   When generating the event transaction, the bus master writes its own ID and a set value of a command requesting the transaction completion notification to the attribute information, and other bus masters until receiving the transaction completion notification from the monitoring device. The monitoring apparatus sends a notification of completion of the transaction to the bus master based on an ID and a command written in the attribute information of the input event transaction. 4. The information processing system according to 4.   When the event master generates the event transaction, the bus master writes in the attribute information a set value of another bus master ID and a command requesting its activation signal, and the monitoring device adds the attribute information of the input event transaction to the attribute information. 5. The information processing system according to claim 4, wherein the activation signal is sent to the other bus master based on the written ID and command.

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