JP2009271610A - Buffer control circuit, buffer circuit and data processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To eliminate a deadlock due to waiting until data are held in a buffer in data processing for stream data or the like. <P>SOLUTION: A FIFO (First-In First-Out) buffer 110 holds the stream data to a stream processing coprocessor from a DMA (Direct Memory Access) control part. A timer circuit 130 counts the time during which a transfer request is continuously output to the DMA control part. When a time-out in the timer circuit 130 is detected by a time-out detection circuit 140, the contents held in a dummy data register 161 is supplied to the FIFO buffer 110. Immediately after DMA transfer is completed (DMA_END=1), dummy data are inserted. During the DMA transfer (DMA_BSY=1), regardless of a time-out signal TMOUT, the insertion of the dummy data is prohibited. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a buffer control circuit, and more particularly to a buffer control circuit, a buffer circuit, and a data processing apparatus that hold data transferred from a memory in a buffer circuit and supply the data to a processing circuit.

  When decoding a variable length code, the data transferred from the memory is temporarily held in a buffer, and the amount of data necessary for the processing is sequentially read from the buffer in bit units. Specifically, a stream processing apparatus is realized as a coprocessor of a CPU (Central Processing Unit), and a FIFO (First-In First-Out) that manages a stream between a DMA (Direct Memory Access) control unit and the coprocessor Provide a buffer. The coprocessor that performs stream processing outputs a stream request and waits until the number of bits to be referred to as a stream is read. Thereby, since the stream is automatically input, it is possible to eliminate the trouble of writing software related to the stream input.

  At this time, if an instruction that uses a stream is executed before the DMA control unit is activated, there is a risk of deadlock. This is because it is premised on that the FIFO buffer is automatically refilled with stream data, so if the stream input stops, the coprocessor will continue to wait for input. The stream request occurs before the DMA control unit is activated when the order is changed due to an instruction description mistake, instruction optimization by the compiler, or out-of-order execution by the processor. There may be a case where a stream request is generated prior to activation because it takes time to update the control register of the control unit.

As a technique for interrupting data transfer processing from a memory, a DMA request control apparatus that forcibly interrupts DMA transfer at the time-out by using a timer has been proposed (for example, see Patent Document 1).
Japanese Patent Laid-Open No. 10-21183 (FIG. 1)

  In the above-described prior art, it is possible to prevent the bus from being occupied for a long time after the DMA transfer is activated. However, even if the DMA transfer is interrupted, the coprocessor keeps waiting until the FIFO buffer is filled with stream data, and the deadlock is not resolved.

  The present invention has been made in view of such a situation, and an object of the present invention is to eliminate a deadlock caused by waiting until data is held in a buffer when processing data such as stream data. To do.

  The present invention has been made to solve the above problems, and a first aspect thereof is a data transfer request circuit for requesting a data transfer circuit to transfer data to a buffer, and data to the buffer. A timer circuit that counts the time during which the data transfer circuit continuously requests the data transfer circuit, and whether or not the time counted by the timer circuit has reached a predetermined time Buffer control comprising a time-out detection circuit for detecting a time-out when the time is reached, and a dummy data supply circuit for supplying dummy data to the buffer instead of data from the data transfer circuit when the time-out is detected Circuit. Thus, when the time counted by the timer circuit reaches a predetermined time, dummy data is supplied to the buffer instead of the data from the data transfer circuit.

  In the first aspect, the time-out detection circuit may be configured such that when the data transfer circuit is in a data transfer completion state with respect to the request, the data transfer circuit is not in a data transfer completion state with respect to the request. It may be determined whether or not the predetermined time has been reached with a shorter time as compared with the case. As a result, when the data transfer is completed, dummy data is supplied to the buffer in a shorter time.

  In this case, the time-out detection circuit detects the time-out when the time counted by the timer circuit becomes non-zero when the data transfer circuit is in a data transfer completion state with respect to the request. Also good. As a result, when the data transfer is completed, dummy data is immediately supplied to the buffer.

  Further, in this first aspect, the dummy data supply circuit does not supply the dummy data to the buffer while the data transfer circuit is busy even when the timeout is detected. Also good. Thus, the dummy data is not supplied to the buffer while the data transfer circuit is busy.

  According to a second aspect of the present invention, there is provided a buffer for holding data, a data transfer request circuit for requesting the data transfer circuit to transfer data to the buffer, and the data transfer to the buffer. A timer circuit that counts the time continuously requested to the transfer circuit, and a time-out when the time counted by the timer circuit reaches a predetermined time by determining whether or not the predetermined time has been reached And a dummy data supply circuit for supplying dummy data to the buffer in place of data from the data transfer circuit when the timeout is detected. Thus, when the time counted by the timer circuit reaches a predetermined time, dummy data is supplied to the buffer instead of the data from the data transfer circuit. In this case, the buffer may be a FIFO buffer.

  The third aspect of the present invention provides a memory, a buffer that holds data, a processing circuit that acquires data from the buffer and performs predetermined data processing, and transfers data from the memory to the buffer. A data transfer circuit for requesting the data transfer circuit to transfer data to the buffer, and continuously requesting the data transfer circuit to transfer data to the buffer. A timer circuit that counts a certain time, a time-out detection circuit that detects whether or not the time counted by the timer circuit has reached a predetermined time and reaches the predetermined time, and the time-out A dummy data supply circuit for supplying dummy data to the buffer instead of data from the data transfer circuit when detected A data processing device comprising a. As a result, when the time counted by the timer circuit reaches a predetermined time, dummy data is supplied to the buffer instead of the data from the data transfer circuit, and the processing circuit performs data processing.

  According to the present invention, when processing data such as stream data, it is possible to achieve an excellent effect that deadlock caused by waiting until data is held in the buffer can be eliminated.

  Next, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a diagram illustrating a configuration example of a stream processing apparatus as an example of a data processing apparatus according to an embodiment of the present invention. The stream processing apparatus includes a CPU (Central Processing Unit) 10, a memory 20, a DMA (Direct Memory Access) control unit 30, a stream processing coprocessor 40, and a stream management unit 100. The CPU 10, the memory 20, and the DMA control unit 30 are mutually connected by a system bus 50. The CPU 10 and the DMA control unit 30 are connected by a peripheral bus 60. The DMA control unit 30 and the stream processing coprocessor 40 are connected by a control line 70.

  The CPU 10 is a processor that performs overall processing of the stream processing apparatus. The CPU 10 accesses the memory 20 via the system bus 50 and controls the DMA control unit 30 via the peripheral bus 60. Further, the CPU 10 is connected to the stream processing coprocessor 40 and issues a coprocessor instruction to the stream processing coprocessor 40 to execute the stream processing.

  The memory 20 is a memory that holds a work area of the CPU 10, and is realized by, for example, an SDRAM (Synchronous Dynamic Random Access Memory). The memory 20 is an example of a memory described in the claims.

  The DMA control unit 30 is a controller that controls DMA transfer with the memory 20. The DMA control unit 30 reads the start address and transfer size set in the control register 42 of the stream processing coprocessor 40 via the control line 70, and communicates with the memory 20 without going through the CPU 10 according to the setting. Perform DMA transfer. The DMA control unit 30 includes a control register 31 therein, and an activation bit for activating DMA transfer is reflected in the control register 31 by the control line 70 from the CPU 10 via the stream processing coprocessor 40. In the embodiment of the present invention, it is assumed that data in the memory 20 is transferred to the stream management unit 100 as stream data. The DMA control unit 30 is an example of a data transfer circuit described in the claims.

  The stream processing coprocessor 40 is a coprocessor that performs stream processing in accordance with a coprocessor instruction from the CPU 10. The stream processing coprocessor 40 includes a shift register 41 therein, and holds the stream data acquired from the stream management unit 100 in the shift register 41. Further, the stream processing coprocessor 40 includes a control register 42, and holds a start address and a transfer size for DMA transfer in the control register 42. The contents of the control register 42 can be referred to by the DMA control unit 30 via the control line 70. The stream processing coprocessor 40 is an example of a processing circuit described in the claims.

  The stream management unit 100 temporarily holds the stream data DMA-transferred by the DMA control unit 30 and supplies the stream data to the stream processing coprocessor 40. The stream management unit 100 includes a FIFO buffer 110 therein, and holds the stream data transferred from the DMA control unit 30 in the FIFO buffer 110.

  FIG. 2 shows the flow of control and data in the stream processing apparatus according to the embodiment of the present invention.

  The CPU 10 issues a coprocessor instruction to the stream processing coprocessor 40 in order to perform stream processing. If the coprocessor instruction issued from the CPU 10 is an instruction that refers to a stream, the stream processing coprocessor 40 outputs a stream request to the stream management unit 100 via the signal line 193. If there is a stream request from the stream processing coprocessor 40 and the internal FIFO buffer 110 is free, the stream management unit 100 sends a transfer request to the DMA control unit 30 via the signal line 103 until there is no free space. Output. The DMA control unit 30 enters a transferable state when the start address and transfer size of the transfer source of the memory 20 are set and the start bit of the control register is set.

  When receiving a transfer request from the stream management unit 100 in the transfer enabled state, the DMA control unit 30 DMA-transfers data to the stream management unit 100 via the signal line 101. In response to the stream request from the stream processing coprocessor 40, the stream management unit 100 supplies stream data to the stream processing coprocessor 40 via the signal line 191.

  FIG. 3 is a diagram illustrating an operation example of the shift register 41 in the stream processing coprocessor 40 according to the embodiment of the present invention. The shift register 41 is a shift register of “2W−1” bits or more (W is an integer), and valid data therein is L bits (L is an integer).

  As shown in FIG. 3A, if “L ≧ W” when performing stream processing, the stream processing coprocessor 40 refers to stream data from the top of the shift register 41 without outputting a stream request. , Execute stream processing. The shift register 41 can refer to only the W bit from the top.

  As shown in FIG. 3B, if “L <W” when performing stream processing, the stream processing coprocessor 40 outputs a stream request to the stream management unit 100. Then, the stream processing coprocessor 40 acquires W-bit data from the stream management unit 100 and writes the acquired W-bit data at the W-bit position immediately after the valid data in the shift register 41. As a result, the bit length L of valid data is updated to “L + W” bits. Thereafter, the stream processing coprocessor 40 refers to the stream data from the top of the shift register 41 and executes the stream processing.

  When a shift of S bits (S is an integer) occurs in the stream processing, the shift register 41 is shifted by S bits, and the bit length L of valid data is updated to “LS” bits. In this way, the stream data is sequentially read from the shift register 41.

  FIG. 4 is a diagram illustrating a configuration example of the stream management unit 100 according to the embodiment of the present invention. The stream management unit 100 includes a FIFO buffer 110, AND circuits 121 and 123, a register 122, a timer circuit 130, a timeout detection circuit 140, an OR circuit 151, and a dummy data supply circuit 160. Yes.

  The FIFO buffer 110 is a first-in first-out buffer that holds data transferred from the DMA control unit 30. The FIFO buffer 110 can hold a plurality of words of W-bit width data. In the FIFO buffer 110, when a write enable (WE) terminal is asserted, data input from a write data (WD) terminal is held. When a read enable (RE) terminal is asserted, data is output from a read data (RD) terminal in the order of input to the write data terminal. When there is no data in the data holding area in the FIFO buffer 110, the empty (EMPTY) terminal is asserted. Further, when there is no space in the FIFO buffer 110 in which data is held, the full (FULL) terminal is asserted. The FIFO buffer 110 is an example of a buffer described in the claims.

  The AND circuit 121 indicates that data can be read when there is a stream request from the stream processing coprocessor 40 via the signal line 193 (DATA_REQ = 1) and the FIFO buffer 110 is not empty (FIFO_EMPTY = 0). Output. The register 122 is a register that holds the output of the logical product circuit 121. When the logical product circuit 121 outputs that data can be read in the immediately preceding cycle, valid data is output via the signal line 192. In addition, the readable terminal of the FIFO buffer 110 is asserted and data reading from the FIFO buffer 110 is instructed. As a result, data is output from the read data terminal of the FIFO buffer 110 and supplied to the signal line 191. When there is a stream request from the stream processing coprocessor 40 via the signal line 193 (DATA_REQ = 1) and the FIFO buffer 110 is free (FIFO_FULL = 0), the logical product circuit 123 passes through the signal line 103. A transfer request is output to the DMA control unit 30 (DMA_REQ = 1).

  The timer circuit 130 is a timer that counts the time during which transfer requests are continuously output to the DMA control unit 30. The timer circuit 130 includes a register 131, an adder 132, and selectors 133 and 134. The register 131 is a register that holds a timer value. The adder 132 adds “1” to the output of the register 131. The selector 133 is a selector that selects the output of the adder 132 when the transfer request is output from the AND circuit 123 and selects the output of the register 131 when the transfer request is not output. The selector 134 is a selector that selects “0” when the timer reset signal TMCNT_RST is asserted from the timeout detection circuit 140, and selects the output value of the selector 133 otherwise. The timer circuit 130 is an example of a timer circuit described in the claims.

  The timeout detection circuit 140 detects a timeout of the timer circuit 130. The timeout detection circuit 140 includes comparators 141 and 142, a selector 143, a logical product circuit 144, a register 145, and a logical sum circuit 146.

  The comparator 141 detects a timeout of the timer circuit 130 with reference to the first timeout value TM1. The comparator 142 detects a time-out of the timer circuit 130 based on the second time-out value TM2. In the embodiment of the present invention, assuming that “TM1> TM2”, for example, TM1 is set to a value larger than “0”, and TM2 is set to “0”. That is, it is assumed that the comparator 141 detects that the value of the timer circuit 130 has reached TM1, and the comparator 142 detects that the value of the timer circuit 130 has become non-zero.

  The selector 143 is a selector that selects the output of the comparator 142 when the DMA transfer end signal DMA_END is asserted from the DMA controller 30, and selects the output of the comparator 141 in other cases. The output of the selector 143 is supplied to the logical product circuit 144 and the logical sum circuit 146 as the timeout signal TMOUT.

  The AND circuit 144 detects that the timeout signal TMOUT is asserted and the DMA transfer in-progress signal DMA_BSY is not asserted from the DMA control unit 30. That is, even if the output of the selector 143 indicates that a timeout has occurred, if the DMA transfer signal indicates busy, the timeout signal is masked. The register 145 is a register that holds the output of the AND circuit 144. The output of the register 145 is supplied to the logical sum circuit 146 and the logical sum circuit 151 as a valid timeout signal TMOUT_WE.

  The OR circuit 146 outputs a reset signal of the timer circuit 130, and is output from the timeout signal TMOUT output from the selector 143, the DMA transfer signal DMA_BSY output from the DMA control unit 30, or the register 145. The logical sum of the valid timeout signals TMOUT_WE is generated. That is, when any one of the timeout signal TMOUT, the DMA transfer signal DMA_BSY, or the valid timeout signal TMOUT_WE is asserted, the reset signal of the timer circuit 130 is asserted.

  The timeout detection circuit 140 is an example of a timeout detection circuit described in the claims.

  The OR circuit 151 outputs a writable signal to the FIFO buffer 110. The logical sum circuit 151 generates a logical sum of the DMA transfer valid signal DMA_ACK output from the DMA control unit 30 or the valid timeout signal TMOUT_WE output from the register 145. That is, when either the DMA transfer valid signal DMA_ACK or the valid timeout signal TMOUT_WE is asserted, the writable terminal of the FIFO buffer 110 is asserted.

  The dummy data supply circuit 160 outputs write data to the FIFO buffer 110. The dummy data supply circuit 160 includes a dummy data register 161 and a selector 162. The dummy data register 161 is a register that holds dummy data supplied to the FIFO buffer 110. The dummy data held in the dummy data register 161 can be an arbitrary value. For example, it is assumed that the dummy data is W bit “0” or W bit “1”. It is more desirable to set the W bit “1” as dummy data because it is expected to detect abnormality by error processing in the stream processing coprocessor 40. The selector 162 selects the data DMA_DATA output from the DMA control unit 30 when the DMA transfer valid signal DMA_ACK output from the DMA control unit 30 is asserted, and otherwise the selector 162 of the dummy data register 161. It is a selector that selects the contents to be held. The dummy data supply circuit 160 is an example of the dummy data supply circuit described in the claims.

  FIG. 5 is a diagram showing a truth table of signals of the stream management unit 100 according to the embodiment of the present invention. When the DMA transfer in progress signal DMA_BSY is “0”, that is, when the DMA transfer is not in progress, the DMA transfer end signal DMA_END is “0”, that is, if the DMA transfer is not completed, The timeout of the timer circuit 130 is detected with reference to the timeout value TM1. That is, when the first timeout value TM1 is reached, the dummy data held in the dummy data register 161 is replenished to the FIFO buffer 110.

  On the other hand, if the DMA transfer end signal DMA_END is “1”, that is, if the DMA transfer is completed when the DMA transfer in progress signal DMA_BSY is “0”, that is, the DMA transfer is not in progress, A timeout of the timer circuit 130 is detected with reference to the second timeout value TM2. In other words, the FIFO buffer 110 is replenished with the dummy data held in the dummy data register 161 with a quick timeout based on the second timeout value TM2 shorter than the first timeout value TM1.

  On the other hand, when the DMA transfer in-progress signal DMA_BSY is “1”, that is, during the DMA transfer, the valid timeout signal TMOUT_WE is not asserted regardless of the timeout signal TMOUT, and the dummy data held in the dummy data register 161. Are not refilled into the FIFO buffer 110.

  FIG. 6 is a diagram illustrating an example of the timing of the stream management unit 100 according to the embodiment of the present invention. In this example, it is assumed that the DMA transfer in-progress signal DMA_BSY is “0” and the DMA transfer end signal DMA_END is “0”.

  When a stream request DATA_REQ is made from the stream processing coprocessor 40 at time T2, the timer circuit 130 starts counting up. When the value of the timer circuit 130 reaches the first timeout value TM1 at time Ti, the timeout signal TMOUT is asserted and the timer reset signal TMCNT_RST is asserted. Thereby, the value of the timer circuit 130 is reset.

  At time Ti + 1, the valid timeout signal TMOUT_WE is asserted, whereby dummy data is replenished to the FIFO buffer 110. In other words, the deadlock is released by forcibly inserting dummy data into the FIFO buffer 110.

  FIG. 7 is a diagram showing another example of the timing of the stream management unit 100 according to the embodiment of the present invention. In this example, it is assumed that the DMA transfer in progress signal DMA_BSY is “1” and the DMA transfer end signal DMA_END is “0”.

  When a stream request DATA_REQ is made from the stream processing coprocessor 40 at time T2, the timer circuit 130 starts counting up. However, since the DMA transfer in-progress signal DMA_BSY is “1”, the register 145 is masked. Therefore, the valid timeout signal TMOUT_WE is not asserted even at time Ti + 1, and the dummy data is not supplemented to the FIFO buffer 110.

  FIG. 8 is a diagram showing still another example of the timing of the stream management unit 100 in the embodiment of the present invention. In this example, it is assumed that the DMA transfer in-progress signal DMA_BSY is “0” and the DMA transfer end signal DMA_END is “1”.

  When a stream request DATA_REQ is made from the stream processing coprocessor 40 at time T2, the timer circuit 130 starts counting up. Since the DMA transfer end signal DMA_END is “1”, the selector 143 selects the output of the comparator 142. In this example, it is assumed that the comparator 142 outputs that the value of the timer circuit 130 is non-zero. Therefore, at time T3, the timeout signal TMOUT is asserted, and the timer reset signal TMCNT_RST is asserted. Thereby, the value of the timer circuit 130 is reset.

  At time T4, the valid timeout signal TMOUT_WE is asserted, whereby dummy data is replenished to the FIFO buffer 110. In other words, since the DMA transfer is completed and no data is sent by the stream request, dummy data is immediately inserted, and unnecessary waiting can be avoided.

  FIG. 9 is a diagram illustrating a control procedure of the stream processing apparatus. In the conventional stream processing apparatus, first, an activation bit is set in the control register of the DMA control unit (step S901), and after activation of the DMA control unit is confirmed (910), the stream processing coprocessor is A stream reference instruction is issued (step S904). That is, in order to confirm (910) the activation of the DMA control unit in the CPU, the activation bit in the control register of the DMA control unit is referred to (step S902), and if the activation bit does not indicate that it has been activated, The reference of the activation bit is repeated until the activation is completed (step S903). Since there is a possibility of an infinite loop in this repetition, it is necessary to detect a timeout by a software counter in order to avoid this.

  On the other hand, in the embodiment of the present invention, confirmation of activation of the DMA control unit (910) is unnecessary, and after the activation bit is set in the control register 31 of the DMA control unit 30 (step S901), A stream reference command can be issued immediately to the stream processing coprocessor 40 (step S904). That is, the occurrence of deadlock is avoided by the stream management unit 100.

  As described above, according to the embodiment of the present invention, the timeout content in the dummy data register 161 can be supplemented to the FIFO buffer 110 by detecting the timeout in the timer circuit 130 by the timeout detection circuit 140. Deadlock can be eliminated. In addition, dummy data is inserted immediately after completion of DMA transfer (DMA_END = 1), so that unnecessary waiting can be avoided. On the other hand, during the DMA transfer (DMA_BSY = 1), the insertion of dummy data can be suppressed regardless of the timeout signal TMOUT.

  In the embodiment of the present invention, it is assumed that information related to DMA transfer is referred to via the control line 70. However, the present invention is not limited to this. For example, these information may be transmitted via the peripheral bus 60. Information may be exchanged.

  Further, the embodiment of the present invention shows an example for embodying the present invention, and has a corresponding relationship with the invention specific matter in the claims as shown below, but is not limited thereto. However, various modifications can be made without departing from the scope of the present invention.

  The processing procedure described in the embodiment of the present invention may be regarded as a method having a series of these procedures, and a program for causing a computer to execute the series of procedures or a recording medium storing the program May be taken as As this recording medium, for example, a recording medium such as a CD (Compact Disc), an MD (MiniDisc), a DVD (Digital Versatile Disk), a memory card, or a Blu-ray Disc (registered trademark) is used. be able to.

It is a figure which shows the structural example of the stream processing apparatus as an example of the data processing apparatus in embodiment of this invention. 2 is a flow of control and data flow in the stream processing apparatus according to the embodiment of the present invention. It is a figure which shows the operation example of the shift register 41 in the stream processing coprocessor 40 in embodiment of this invention. It is a figure which shows the example of 1 structure of the stream management part 100 in embodiment of this invention. It is a figure which shows the truth table of the signal of the stream management part 100 in embodiment of this invention. It is a figure which shows an example of the timing of the stream management part 100 in embodiment of this invention. It is a figure which shows the other example of the timing of the stream management part 100 in embodiment of this invention. It is a figure which shows the further another example of the timing of the stream management part 100 in embodiment of this invention. It is a figure which shows the control procedure of a stream processing apparatus.

Explanation of symbols

10 CPU
DESCRIPTION OF SYMBOLS 20 Memory 30 DMA control part 31 Control register 40 Stream processing coprocessor 41 Shift register 42 Control register 50 System bus 60 Peripheral bus 100 Stream management part 110 FIFO buffer 121 AND circuit 122,131,145 register 123 AND circuit 130 Timer circuit 132 Adder 133, 134, 143, 162 Selector 140 Timeout detection circuit 141, 142 Comparator 144 AND circuit 146, 151 OR circuit 160 Dummy data supply circuit 161 Dummy data register

Claims (7)

A data transfer request circuit that requests the data transfer circuit to transfer data to the buffer;
A timer circuit that counts the time for which the data transfer circuit is continuously requested to transfer data to the buffer;
A time-out detection circuit that determines whether a time counted by the timer circuit has reached a predetermined time and detects a time-out when the predetermined time is reached;
A buffer control circuit comprising: a dummy data supply circuit for supplying dummy data to the buffer instead of data from the data transfer circuit when the timeout is detected; The time-out detection circuit has a shorter time when the data transfer circuit is in a data transfer completion state with respect to the request than when the data transfer circuit is not in a data transfer completion state with respect to the request. 2. The buffer control circuit according to claim 1, wherein it is determined whether or not the predetermined time has been reached as the predetermined time. 3. The buffer control according to claim 2, wherein the time-out detection circuit detects the time-out when the time counted by the timer circuit becomes non-zero when the data transfer circuit is in a data transfer completion state with respect to the request. circuit. The buffer control circuit according to claim 1, wherein the dummy data supply circuit does not supply the dummy data to the buffer while the data transfer circuit is in a busy state even when the timeout is detected. A buffer to hold the data,
A data transfer request circuit for requesting the data transfer circuit to transfer data to the buffer;
A timer circuit that counts the time for which the data transfer circuit is continuously requested to transfer data to the buffer;
A time-out detection circuit that determines whether a time counted by the timer circuit has reached a predetermined time and detects a time-out when the predetermined time is reached;
A buffer circuit comprising: a dummy data supply circuit for supplying dummy data to the buffer instead of data from the data transfer circuit when the timeout is detected;   The buffer circuit is a FIFO buffer. Memory,
A buffer to hold the data,
A processing circuit for obtaining data from the buffer and performing predetermined data processing;
A data transfer circuit for transferring data from the memory to the buffer;
A data transfer request circuit for requesting the data transfer circuit to transfer data to the buffer;
A timer circuit that counts the time for which the data transfer circuit is continuously requested to transfer data to the buffer;
A time-out detection circuit that determines whether a time counted by the timer circuit has reached a predetermined time and detects a time-out when the predetermined time is reached;
A data processing device comprising: a dummy data supply circuit that supplies dummy data to the buffer instead of data from the data transfer circuit when the timeout is detected.

Images